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"Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using ..."

Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng (2000)

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DOI: 10.1109/4.839918

access: closed

type: Journal Article

metadata version: 2022-04-13

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Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng:
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops. IEEE J. Solid State Circuits 35(4): 583-592 (2000)

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