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ORCIDNaoki Kuroda
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2000 – 2009
- 2005
[j3]Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi
:
A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process. IEEE J. Solid State Circuits 40(5): 1200-1207 (2005)- [j2]Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto:
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits 40(11): 2296-2304 (2005) - 2000
- [j1]Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita:
An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM). IEEE J. Solid State Circuits 35(11): 1668-1672 (2000)
1990 – 1999
- 1995
- [c1]Takao Hinamoto, Shuji Karino, Naoki Kuroda:
Error Spectrum Shaping in 2-D Digital Filters. ISCAS 1995: 348-351
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