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ORCIDRichard C. Jaeger
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- affiliation: Auburn University, USA
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2010 – 2019
- 2018
[c16]Richard C. Jaeger, Jeffrey C. Suhling:
First and Second Order Piezoresistive Characteristics of CMOS FETs: Weak through Strong Inversion. ESSDERC 2018: 126-129- 2014
- [j16]Jianjun Yu, Feng Zhao, Joseph Cali, Fa Foster Dai, Desheng Ma, Xueyang Geng, Yuehai Jin, Yuan Yao, Xin Jin, J. David Irwin, Richard C. Jaeger:
An X-Band Radar Transceiver MMIC with Bandwidth Reduction in 0.13 µm SiGe Technology. IEEE J. Solid State Circuits 49(9): 1905-1915 (2014) - [c15]Safina Hussain, Richard C. Jaeger, Jeffrey C. Suhling:
Current dependence of the piezoresistive coefficients of CMOS FETs on (100) silicon. ESSDERC 2014: 74-77 - 2011
- [j15]Desheng Ma, Fa Foster Dai, Richard C. Jaeger, J. David Irwin:
An X- and Ku-Band Wideband Recursive Receiver MMIC With Gain-Reuse. IEEE J. Solid State Circuits 46(3): 562-571 (2011) - 2010
- [j14]Xueyang Geng, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC. IEEE J. Solid State Circuits 45(2): 300-313 (2010) - [j13]Jianjun Yu, Fa Foster Dai, Richard C. Jaeger:
A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS Technology. IEEE J. Solid State Circuits 45(4): 830-842 (2010) - [j12]Xueyang Geng, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 μ m SiGe BiCMOS Technology. IEEE J. Solid State Circuits 45(5): 944-954 (2010)
2000 – 2009
- 2009
- [j11]Dayu Yang, Foster F. Dai, Weining Ni, Yin Shi, Richard C. Jaeger:
Delta-Sigma Modulation for Direct Digital Frequency Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 793-802 (2009) - 2008
- [j10]Xuefeng Yu, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 µm SiGe BiCMOS Technology. IEEE J. Solid State Circuits 43(6): 1384-1393 (2008) - [j9]Yuan Yao, Foster F. Dai, Richard C. Jaeger, John D. Cressler:
A 12-Bit Cryogenic and Radiation-Tolerant Digital-to-Analog Converter for Aerospace Extreme Environment Applications. IEEE Trans. Ind. Electron. 55(7): 2810-2819 (2008) - [c14]Yin Shi, Foster F. Dai, Jun Yan, Xueqing Hu, Hua Xu, Ming Gu, Xuelian Zhang, Qiming Xu, Bei Chen, Fangxiong Chen, Peng Yu, Heping Ma, Fang Yuan, Richard C. Jaeger:
A multifunction transceiver RFIC for 802.11a/b/g WLAN and DVB-H applications. CICC 2008: 249-252 - [c13]Yin Shi, Fa Foster Dai, Jun Yan, Hua Xu, Xuelian Zhang, Heping Ma, Fang Yuan, Xin Guan, Richard C. Jaeger:
A fully integrated zero-IF mobile TV tuner RFIC for S-band CMMB application. CICC 2008: 253-256 - [c12]Xuefeng Yu, Fa Foster Dai, Dayu Yang, J. David Irwin, Richard C. Jaeger:
An X/Ku-band frequency synthesizer using a 9-Bit quadrature DDS. CICC 2008: 491-494 - [c11]Xueyang Geng, Xuefeng Yu, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DAC. ESSCIRC 2008: 362-365 - 2006
- [j8]Fa Foster Dai, Weining Ni, Yin Shi, Richard C. Jaeger:
A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC. IEEE J. Solid State Circuits 41(4): 839-850 (2006) - [c10]Dayu Yang, Weining Ni, Fa Foster Dai, Yin Shi, Richard C. Jaeger:
Delta-Sigma Modulation in Direct Digital Frequency Synthesis. CICC 2006: 523-526 - [c9]Oimins Xu, Xueqing Hu, Pens Gao, Jun Yan, Yin Shi, Foster F. Dai, Richard C. Jaeger:
A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver. ISCAS 2006 - [c8]Yuan Yao, Xuefeng Yu, Foster F. Dai, Richard C. Jaeger:
A 12-bit current steering DAC for cryogenic applications. ISCAS 2006 - 2005
- [c7]Vasanth Kakani, Foster F. Dai, Richard C. Jaeger:
An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks. ISCAS (2) 2005: 1178-1181 - [c6]Foster F. Dai, Shengfang Wei, Richard C. Jaeger:
Integrated blind electronic equalizer for fiber dispersion compensation. ISCAS (6) 2005: 5750-5753 - 2004
- [c5]Malinky Ghosh, Lakshmi S. J. Chimakurthy, Foster F. Dai, Richard C. Jaeger:
A novel DDS architecture using nonlinear ROM addressing with improved compression ratio and quantisation noise. ISCAS (2) 2004: 705-708 - [c4]Vasanth Kakani, Foster F. Dai, Richard C. Jaeger:
Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits. ISCAS (2) 2004: 869-872 - 2000
- [j7]Richard C. Jaeger, Jeffrey C. Suhling, Ramanathan Ramani, Arthur T. Bradley, Jianping Xu:
CMOS stress sensors on [100] silicon. IEEE J. Solid State Circuits 35(1): 85-95 (2000)
1990 – 1999
- 1999
- [j6]Bogdan M. Wilamowski, Richard C. Jaeger, M. Okyay Kaynak:
Neuro-fuzzy architecture for CMOS implementation. IEEE Trans. Ind. Electron. 46(6): 1132-1136 (1999) - [c3]Arthur T. Bradley, Richard C. Jaeger, Jeffrey C. Suhling, Y. Zou:
Test chips for die stress characterization using arrays of CMOS sensors. CICC 1999: 147-150 - 1996
- [j5]Lakshmi S. Vempati, John D. Cressler, Jeffrey Babcock, Richard C. Jaeger, David L. Harame:
Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors. IEEE J. Solid State Circuits 31(10): 1458-1467 (1996) - [c2]Bogdan M. Wilamowski, Richard C. Jaeger, Mary Lou Padgett, Lawrence J. Myers:
CMOS implementation of a pulse-coupled neuron cell. ICNN 1996: 986-990 - [c1]Bogdan M. Wilamowski, Richard C. Jaeger:
Implementation of RBF type networks by MLP networks. ICNN 1996: 1670-1675 - 1992
- [j4]Travis N. Blalock, Richard C. Jaeger:
A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier. IEEE J. Solid State Circuits 27(4): 618-625 (1992) - 1991
- [j3]Travis N. Blalock, Richard C. Jaeger:
A high-speed clamped bit-line current-mode sense amplifier. IEEE J. Solid State Circuits 26(4): 542-548 (1991)
1980 – 1989
- 1986
- [j2]Richard C. Jaeger:
Computer-Aided Design of One-Dimensional MOSFET Impurity Profiles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1): 198-203 (1986) - 1983
- [j1]Richard C. Jaeger, Fritz H. Gaensslen, Sherra E. Diehl:
An Efficient Numerical Algorithm for Simulation of MOS Capacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(2): 111-116 (1983)
Coauthor Index
aka: Fa Foster Dai
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