"Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of ..."

Kenichi Ohhata et al. (2000)

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DOI: 10.1109/4.839916

access: closed

type: Journal Article

metadata version: 2022-04-08

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Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta:
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. IEEE J. Solid State Circuits 35(4): 564-571 (2000)

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