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"1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded ..."

Osamu Takahashi et al. (2000)

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DOI: 10.1109/4.881214

access: closed

type: Journal Article

metadata version: 2022-04-13

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Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki:
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits 35(11): 1673-1679 (2000)

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