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"Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing ..."

Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur (2011)

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DOI: 10.1109/TVLSI.2009.2031650

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/JeyasinghBA11
Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur:
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 295-304 (2011)

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