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"A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 ..."

Won-Joo Yun et al. (2011)

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DOI: 10.1109/TVLSI.2010.2053395

access: closed

type: Journal Article

metadata version: 2020-03-11

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Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim:
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1718-1722 (2011)

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