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ORCIDYoung-Jung Choi
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2010 – 2019
- 2013
[c15]Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim:
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. ISSCC 2013: 312-313- 2012
- [j4]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. IEEE J. Solid State Circuits 47(1): 131-140 (2012) - [j3]Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits 47(6): 1436-1447 (2012) - [c14]Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim:
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC 2012: 48-50 - 2011
- [c13]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. ISSCC 2011: 502-504 - 2010
- [c12]Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih:
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS 2010: 3861-3864 - [c11]Dongsuk Shin, Joo-Hwan Cho, Young-Jung Choi, Byong-Tae Chung:
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster. SoCC 2010: 79-82
2000 – 2009
- 2009
- [j2]Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Young-Jung Choi, Suki Kim:
Coverage expandable current type code controlled DCC with TDC-based range selector. IEICE Electron. Express 6(5): 205-210 (2009) - [c10]Jabeom Koo
, Gil-Su Kim, Junyoung Song, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. CICC 2009: 717-720 - [c9]Dongsuk Shin, Jabeom Koo, Won-Joo Yun, Young-Jung Choi, Chulwoo Kim:
A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter. ISCAS 2009: 1-4 - [c8]Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung:
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. ISSCC 2009: 140-141 - 2008
- [c7]Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim:
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. ESSCIRC 2008: 82-85 - [c6]Young-Jung Choi, Ha-Joong Park, Xingang Liu, Kook-Yeol Yoo, Ho-Youl Jung:
SDTV Quality Assessment Using Energy Distribution of DCT Coefficients. ICESS 2008: 118-125 - [c5]Dong-Uk Lee, Shin-Deok Kang, Nak-Kyu Park, Hyun-Woo Lee, Young-Kyoung Choi, Jung-Woo Lee, Seung-Wook Kwack, Hyeong-Ouk Lee, Won-Joo Yun, Sang-Hoon Shin, Kwan-Weon Kim, Young-Jung Choi, Ye Seok Yang:
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. ISSCC 2008: 280-281 - [c4]Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang:
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. ISSCC 2008: 282-283 - 2007
- [j1]Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn:
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. IEEE J. Solid State Circuits 42(11): 2369-2377 (2007) - [c3]Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. ISSCC 2007: 184-595 - [c2]Young-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim:
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver. ISSCC 2007: 408-611 - 2006
- [c1]Dong-Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih:
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. ISSCC 2006: 547-556
Coauthor Index
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