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"A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High ..."

Arnoud P. van der Wel, Gerrit den Besten (2012)

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DOI: 10.1109/JSSC.2012.2191318

access: closed

type: Journal Article

metadata version: 2020-08-30

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Arnoud P. van der Wel, Gerrit den Besten:
A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS. IEEE J. Solid State Circuits 47(7): 1768-1775 (2012)

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