"A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V ..."

Harold Pilo et al. (2012)

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DOI: 10.1109/JSSC.2011.2164730

access: closed

type: Journal Article

metadata version: 2022-03-29

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Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic:
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. IEEE J. Solid State Circuits 47(1): 97-106 (2012)

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