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Ki Chul Chun
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2020 – today
- 2021
- [j9]Jaewon Park, Jae Hoon Lee, Sang-Kil Park, Ki Chul Chun, Kyomin Sohn, Sungho Kang:
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process. IEEE Access 9: 33487-33497 (2021) - [j8]Ki Chul Chun, Yong-Ki Kim, Yesin Ryu, Jaewon Park, Chi Sung Oh, Young-Yong Byun, So-Young Kim, Dong-Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung-Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Sooyoung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Jung-Bae Lee:
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. IEEE J. Solid State Circuits 56(1): 199-211 (2021) - 2020
- [c9]Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim, So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sang-uhn Cha, Dong-Hak Shin, Jungyu Lee, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yong-Sik Park, Kijun Lee, Myung-Kyu Lee, Seungduk Baek, Junyong Noh, Jae-Wook Lee, Seungseob Lee, Sooyoung Kim, Bo-Tak Lim, Seouk-Kyu Choi, Jin-Guk Kim, Hye-In Choi, Hyuk-Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang-Il Park, Jung-Bae Lee:
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. ISSCC 2020: 330-332
2010 – 2019
- 2018
- [c8]Ki Chul Chun, Yonggyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, Inkyu Moon, Young-Ju Kim, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung-Bum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. ISSCC 2018: 206-208 - 2014
- [j7]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications. IEEE J. Solid State Circuits 49(8): 1861-1871 (2014) - 2013
- [j6]Ki Chul Chun, Hui Zhao, Jonathan D. Harms, Tony Tae-Hyoung Kim, Jianping Wang, Chris H. Kim:
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory. IEEE J. Solid State Circuits 48(2): 598-610 (2013) - [j5]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme. IEEE J. Solid State Circuits 48(5): 1302-1314 (2013) - [j4]Wei Zhang, Ki Chul Chun, Chris H. Kim:
A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2030-2038 (2013) - [c7]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications. CICC 2013: 1-4 - 2012
- [j3]Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim:
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. IEEE J. Solid State Circuits 47(2): 547-559 (2012) - [j2]Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. IEEE J. Solid State Circuits 47(10): 2517-2526 (2012) - [c6]Wei Zhang, Ki Chul Chun, Chris H. Kim:
A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode. CICC 2012: 1-4 - [c5]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme. VLSIC 2012: 130-131 - 2011
- [j1]Ki Chul Chun, Pulkit Jain, Jung-Hwa Lee, Chris H. Kim:
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. IEEE J. Solid State Circuits 46(6): 1495-1505 (2011) - [c4]Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. ISSCC 2011: 506-507 - 2010
- [c3]Ki Chul Chun, Pulkit Jain, Chris H. Kim:
Logic-compatible embedded DRAM design for memory intensive low power systems. ISCAS 2010: 277-280 - [c2]Wei Zhang, Ki Chul Chun, Chris H. Kim:
Variation aware performance analysis of gain cell embedded DRAMs. ISLPED 2010: 19-24
2000 – 2009
- 2009
- [c1]Ki Chul Chun, Pulkit Jain, Chris H. Kim:
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ISLPED 2009: 119-120
Coauthor Index
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