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ORCIDDinesh Patil
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2020 – today
- 2024
[i1]Vatsal Kedia, Vivek S. Pinnamaraju, Dinesh Patil:
Model fusion for efficient learning of nonlinear dynamical systems. CoRR abs/2406.03752 (2024)- 2023
- [c8]Karl Kaiser, Dinesh Patil, Edith Beigné:
A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML. VLSI Technology and Circuits 2023: 1-2
2010 – 2019
- 2019
- [j5]Ryan Rivas
, Dinesh Patil, Vagelis Hristidis, Joseph R. Barr, Narayanan Srinivasan:
The impact of colleges and hospitals to local real estate markets. J. Big Data 6: 7 (2019) - 2012
- [j4]Frankie Liu, Dinesh Patil, Jon K. Lexau, Philip Amberg, Michael Dayringer, Jonathan Gainsley, Hesam Fathi Moghadam, Xuezhe Zheng, John E. Cunningham, Ashok V. Krishnamoorthy, Elad Alon, Ron Ho:
10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS. IEEE J. Solid State Circuits 47(9): 2049-2067 (2012) - 2011
- [c7]Philip Amberg, Frankie Liu, Michael Dayringer, Jon K. Lexau, Dinesh Patil, Jonathan Gainsley, Hesam Fathi Moghadam, Elad Alon, Xuezhe Zheng, John E. Cunningham, Ashok V. Krishnamoorthy, Ron Ho:
Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS. A-SSCC 2011: 29-32 - 2010
- [j3]Ron Ho, Frankie Liu, Dinesh Patil, Xuezhe Zheng, Guoliang Li, Ivan Shubin, Elad Alon, Jon K. Lexau, Herb Schwetman, John E. Cunningham, Ashok V. Krishnamoorthy:
Optical Interconnect for High-End Computer Systems. IEEE Des. Test Comput. 27(4): 10-19 (2010) - [c6]Deepak Jeswani, Nakul Korde, Dinesh Patil, Maitreya Natu, John Augustine:
Probe station selection algorithms for fault management in computer networks. COMSNETS 2010: 1-9 - [c5]Tamer A. Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon K. Lexau, Chih-Kong Ken Yang, Ron Ho:
Clocking Links in Multi-chip Packages: A Case Study. Hot Interconnects 2010: 96-103
2000 – 2009
- 2008
- [c4]Steven Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, David Money Harris, Dinesh Patil:
Energy-delay tradeoffs in 32-bit static shifter designs. ICCD 2008: 626-632 - [c3]Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz:
Processor Performance Modeling using Symbolic Simulation. ISPASS 2008: 127-138 - 2007
- [c2]Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman:
Robust Energy-Efficient Adder Topologies. IEEE Symposium on Computer Arithmetic 2007: 16-28 - 2005
- [j2]Stephen P. Boyd, Seung-Jean Kim, Dinesh Patil, Mark Horowitz:
Digital Circuit Optimization via Geometric Programming. Oper. Res. 53(6): 899-932 (2005) - [j1]Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz:
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. IEEE J. Solid State Circuits 40(1): 261-275 (2005) - [c1]Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd:
A New Method for Design of Robust Digital Circuits. ISQED 2005: 676-681
Coauthor Index
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