Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an ..."

Ping Lu, Antonio Liscidini, Pietro Andreani (2012)

> Home

Details and statistics

DOI: 10.1109/JSSC.2012.2191676

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/LuLA12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/LuLA12
Ping Lu, Antonio Liscidini, Pietro Andreani:
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps. IEEE J. Solid State Circuits 47(7): 1626-1635 (2012)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.