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ORCIDJung-Bae Lee
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2020 – today
- 2021
[j8]Ki Chul Chun
, Yong-Ki Kim, Yesin Ryu, Jaewon Park, Chi Sung Oh, Young-Yong Byun, So-Young Kim, Dong-Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung-Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Sooyoung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Jung-Bae Lee:
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. IEEE J. Solid State Circuits 56(1): 199-211 (2021)- [j7]Chang-Kyo Lee, Hyung-Joon Chi, Jin-Seok Heo, Junghwan Park, Jin-Hun Jang, Dongkeon Lee, Jaehoon Jung, Dong-Hun Lee, Dae-Hyun Kim, Kihan Kim, Sang-Yun Kim, Dukha Park, Youngil Lim, Geuntae Park, Seungjun Lee, Seungki Hong, Dae-Hyun Kwon, Isak Hwang, Byongwook Na, Kyungryun Kim, Seouk-Kyu Choi, Hye-In Choi, Hangi-Jung, Wonil Bae, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee:
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. IEEE J. Solid State Circuits 56(1): 212-224 (2021) - [c13]Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae-Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chanyoung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee:
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. ISSCC 2021: 346-348 - 2020
- [j6]Kyung-Soo Ha, Seungseob Lee, Youn-Sik Park, Hyuck-Joon Kwon, Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Young-Hwa Kim, Young Hoon Son, Byongwook Na:
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. IEEE J. Solid State Circuits 55(1): 157-166 (2020) - [c12]Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim, So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sang-uhn Cha, Dong-Hak Shin, Jungyu Lee, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yong-Sik Park, Kijun Lee, Myung-Kyu Lee, Seungduk Baek, Junyong Noh, Jae-Wook Lee, Seungseob Lee, Sooyoung Kim, Bo-Tak Lim, Seouk-Kyu Choi, Jin-Guk Kim, Hye-In Choi, Hyuk-Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang-Il Park, Jung-Bae Lee:
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. ISSCC 2020: 330-332 - [c11]Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim, Dukha Park, Kihan Kim, Sang-Yun Kim, Jinsol Park, Hyunyoon Cho, Sukhyun Lim, YeonKyu Choi, Youngil Lim, Daesik Moon, Geuntae Park, Jin-Hun Jang, Kyungho Lee, Isak Hwang, Cheol Kim, Younghoon Son, Gil-Young Kang, Kiwon Park, Seungjun Lee, Su-Yeon Doo, Chang-Ho Shin, Byongwook Na, Ji-Suk Kwon, Kyung Ryun Kim, Hye-In Choi, Seouk-Kyu Choi, Soobong Chang, Wonil Bae, Hyuck-Joon Kwon, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee:
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. ISSCC 2020: 382-384
2010 – 2019
- 2019
- [c10]Jin-Seok Heo, Kihan Kim, Dong-Hoon Lee, Chang-Kyo Lee, Daesik Moon, Kiho Kim, Jin-Hyeok Baek, Sung-Woo Yoon, Hui-Kap Yang, Kyungryun Kim, Youngjae Kim, Bokgue Park, Su-Jin Park, Joung-Wook Moon, Jae-Hyung Lee, Yun-Sik Park, Soobong Jang, Seok-Hun Hyun, Hyuck-Joon Kwon, Jung-Hwan Choi, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee:
A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. VLSI Circuits 2019: 114- - 2014
- [j5]Sang-Hye Chung, Young-Ju Kim, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Lee-Sup Kim:
A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 153-157 (2014) - [c9]Tae-Young Oh, Hoeju Chung, Young-Chul Cho, Jang-Woo Ryu, Kiwon Lee, Changyoung Lee, Jin-Il Lee, Hyoung-Joo Kim, Min-Soo Jang, Gong-Heum Han, Kihan Kim, Daesik Moon, Seung-Jun Bae, Joon-Young Park, Kyung-Soo Ha, Jaewoong Lee, Su-Yeon Doo, Jung-Bum Shin, Chang-Ho Shin, Kiseok Oh, Doo-Hee Hwang, Taeseong Jang, Chulsung Park, Kwang-Il Park, Jung-Bae Lee, Joo-Sun Choi:
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. ISSCC 2014: 430-431 - 2013
- [j4]Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi:
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. IEEE J. Solid State Circuits 48(1): 168-177 (2013) - [c8]Ji-Hwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, Lee-Sup Kim:
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. ISSCC 2013: 410-411 - 2012
- [j3]Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo-Sun Choi, Young-Hyun Jun:
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. IEEE J. Solid State Circuits 47(1): 107-116 (2012) - [c7]Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung-Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Young Hoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. ISSCC 2012: 44-46 - [c6]Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, Jae-Yoon Sim:
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. ISSCC 2012: 136-138 - 2011
- [c5]Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun:
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. ISSCC 2011: 496-498
2000 – 2009
- 2009
- [j2]Young-Chan Jang, Hoeju Chung, Youngdon Choi, Hwan-Wook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Yun Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Jei-Hwan Yoo, Changhyun Kim:
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. IEEE J. Solid State Circuits 44(11): 2987-2998 (2009) - [c4]Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology. ISSCC 2009: 130-131 - [c3]Xueyi Yu, Woogeun Rhee, Zhihua Wang, Jung-Bae Lee, Changhyun Kim:
A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation. ISSCC 2009: 398-399 - 2007
- [c2]Sang-Young Cho, Yoojin Chung, Jung-Bae Lee:
Virtual Development Environment Based on SystemC for Embedded Systems. International Conference on Computational Science (4) 2007: 949-956 - 2006
- [j1]Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho:
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. IEEE J. Solid State Circuits 41(4): 831-838 (2006) - 2005
- [c1]Yu-Kyung Kang, Suk-hyung Hwang, Hae Sool Yang, Jung-Bae Lee, Hee-Chul Choi, Hyun-Wook Wee, Dong-Soon Kim:
CEB: Class Quality Evaluator for BlueJ. ICCSA (3) 2005: 938-944
Coauthor Index
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