15. VLSI Design / ASP-DAC 2002: Bangalore, India

Keynote Talks

• Biswadip Mitra:
  Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. 3-4
  
• Kazuo Yano:
  LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era. 5
  
• Aart J. de Geus:
  Electronic Industry on Fire: How to Survive and Thrive. 6
  
• Martin F. H. Schuurmans:
  Digital Watermarking. 7-
  

Tutorials

• Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan:
  Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). 11-13
  
• Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven:
  System-Level Design of Embedded Media Systems (Tutorial Abstract). 14-15
  
• Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta:
  Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). 16-17
  
• M. V. Atre, P. S. Subramanian, H. Narayanan:
  Mathematical Methods in VLSI (Tutorial Abstract). 18-19
  
• Vishwani D. Agrawal, Michael L. Bushnell:
  Electronic Testing for SOC Designers (Tutorial Abstract). 20
  
• Luciano Lavagno, Sujit Dey, Rajesh K. Gupta:
  Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). 21-23
  
• R. Lal, P. R. Apte, K. N. Bhat, G. Bose, S. Chandra, D. K. Sharma:
  MEMS: Technology, Design, CAD and Applications (Tutorial Abstract). 24-25
  
• Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside:
  Logic Design of Asynchronous Circuits (Tutorial Abstract). 26-
  

Low Power I

• David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Evaluating Run-Time Techniques for Leakage Power Reduction. 31-38
  
• Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha:
  Topological Analysis for Leakage Prediction of Digital Circuits. 39-44
  
• Rahul Kumar, C. P. Ravikumar:
  Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. 45-50
  
• Fei Li, Lei He, Kewal K. Saluja:
  Estimation of Maximum Power-Up Current. 51-
  

Interconnects and Technology I

• Joong-Ho Kim, Erdem Matoglu, Jinwoo Choi, Madhavan Swaminathan:
  Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method. 59-64
  
• Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
  Dynamic Noise Analysis with Capacitive and Inductive Coupling. 65-70
  
• Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata:
  Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. 71-76
  
• Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu:
  Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. 77-
  

Synthesis I

• Rupesh S. Shelar, Sachin S. Sapatnekar:
  An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. 87-92
  
• Hiroshi Saito, Alex Kondratyev, Takashi Nanya:
  Design of Asynchronous Controllers with Delay Insensitive Interface. 93-98
  
• Debasis Samanta, Nishant Sinha, Ajit Pal:
  Synthesis of High Performance Low Power Dynamic CMOS Circuits. 99-104
  
• Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri:
  Improvement of ASIC Design Processes. 105-
  

Low Power II

• Haris Lekatsas, Jörg Henkel:
  ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. 113-120
  
• Rung-Bin Lin, Chi-Ming Tsai:
  Weight-Based Bus-Invert Coding for Low-Power Applications. 121-125
  
• Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram:
  Software-Only Bus Encoding Techniques for an Embedded System. 126-131
  
• Payam Heydari, Massoud Pedram:
  Interconnect Energy Dissipation in High-Speed ULSI Circuits. 132-
  

Interconnects and Technology II

• N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell:
  Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. 141
  
• P. K. Datta, S. Sanyal, D. Bhattacharya:
  Losses in Multilevel Crossover in VLSI Interconnects. 142-146
  
• Qinwei Xu, Pinaki Mazumder:
  Rational ABCD Modeling of High-Speed Interconnects. 147-
  

Synthesis II

• Kuo-Hsing Cheng, Shun-Wen Cheng:
  Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. 155-159
  
• Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
  A New Synthesis of Symmetric Functions. 160-165
  
• Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
  Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. 166-171
  
• D. Sarkar:
  Register Transfer Operation Analysis during Data Path Verification. 172-
  

Low Power III

• Ashok K. Murugavel, N. Ranganathan:
  A Real Delay Switching Activity Simulator Based on Petri Net Modeling. 181-186
  
• Sanjukta Bhanja, N. Ranganathan:
  Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. 187-192
  
• Debasis Samanta, Ajit Pal:
  Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. 193-198
  
• Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti:
  Minimizing Energy Consumption for High-Performance Processing. 199-
  

Interconnects and Technology III

• A. B. Bhattacharyya, Shrutin Ulman:
  PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. 207-212
  
• Peter M. Lee, Shinji Ito, Takeaki Hashimoto, Junji Sato, Tomomasa Touma, Goichi Yokomizo:
  A Parallel and Accelerated Circuit Simulator with Precise Accuracy. 213-218
  
• Srinath R. Naidu:
  Timing Yield Calculation Using an Impulse-Train Approach. 219-224
  
• H. C. Srinivasaiah, Navakanta Bhat:
  Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. 225-
  

Synthesis III

• Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar:
  Exploring the Number of Register Windows in ASIP Synthesis. 233-238
  
• Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr:
  Architecture Implementation Using the Machine Description Language LISA. 239-244
  
• Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
  A Framework for Design Space Exploration of Parameterized VLSI Systems. 245-250
  
• S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri:
  An Evolutionary Scheme for Cosynthesis of Real-Time Systems. 251-
  

Low Power IV

• Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi:
  Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. 261-267
  
• Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura:
  A Power Minimization Technique for Arithmetic Circuits by Cell Selection. 268-273
  
• Yunsi Fei, Niraj K. Jha:
  Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. 274-281
  
• Tohru Ishihara, Kunihiro Asada:
  An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. 282-287
  
• Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu:
  Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. 288-
  

Interconnects and Technology IV

• S. Natarajan, A. Marshall:
  Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI. 297-298
  
• Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh:
  Transistor Flaring in Deep Submicron-Design Considerations. 299-304
  
• Shuzhou Fang, Zeyi Wang, Xianlong Hong:
  A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. 305-310
  
• Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh:
  Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. 311-316
  
• Maryam Shojaei Baghini, Madhav P. Desai:
  Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. 317-
  

Synthesis IV

• P. Klapproth:
  Embedded Tutorial: General Architectural Concepts for IP Core Re-Use. 325-
  
• Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri:
  Framework for Synthesis of Virtual Pipelines. 326-331
  
• Junyu Peng, Samar Abdi, Daniel Gajski:
  Automatic Model Refinement for Fast Architecture Exploration. 332-337
  
• Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck:
  Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. 338-344
  
• Li Shang, Niraj K. Jha:
  Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. 345-
  

Analog Design

• Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida:
  A Design of Analog C-Matrix Circuits Used for Signal/Data Processing. 355-359
  
• Debapriya Sahu:
  A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. 360-365
  
• Biranchinath Sahu, Aloke K. Dutta:
  Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach. 366-371
  
• Jens Lienig, Goeran Jerke, Thorsten Adler:
  Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. 372-
  

Layout I

• Wei Chen, Massoud Pedram, Premal Buch:
  Buffered Routing Tree Construction under Buffer Placement Blockages. 381-386
  
• Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
  Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. 387-392
  
• Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin:
  An Adaptive Interconnect-Length Driven Placer. 393-398
  
• Stelian Alupoaei, Srinivas Katkoori:
  Net Clustering Based Macrocell Placement. 399-
  

Synthesis and Verification

• Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac:
  High-Level Synthesis with SIMD Units. 407-413
  
• J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir:
  A Heuristic for Clock Selection in High-Level Synthesis. 414-419
  
• Indradeep Ghosh, Krishna Sekar, Vamsi Boppana:
  Design for Verification at the Register Transfer Level. 420-425
  
• Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya:
  Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design. 426-
  

VLSI Architecture I

• Kavish Seth, S. Srinivasan:
  VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. 435-440
  
• Hak-soo Yu, Jacob A. Abraham:
  An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. 441-446
  
• Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout:
  Architecture and Design of a High Performance SRAM for SOC Design. 447-451
  
• Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
  VLSI Architecture for a Flexible Motion Estimation with Parameters. 452-457
  
• Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
  Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. 458-
  

Layout II

• Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
  Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. 467-472
  
• Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
  An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. 473-478
  
• Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita:
  Simultaneous Circuit Transformation and Routing. 479-483
  
• Chunhong Chen:
  Probabilistic Analysis of Rectilinear Steiner Trees. 484-488
  
• Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
  Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. 489-
  

Test and Validation

• Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
  A Novel Method to Improve the Test Efficiency of VLSI Tests. 499-504
  
• Sandeep Koranne:
  On Test Scheduling for Core-Based SOCs. 505-510
  
• Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy:
  Constraint Driven Pin Mapping for Concurrent SOC Testing. 511-516
  
• Katarzyna Radecka, Zeljko Zilic:
  Identifying Redundant Wire Replacements for Synthesis and Verification. 517-523
  
• Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi:
  Property-Specific Testbench Generation for Guided Simulation. 524-
  

VLSI Architecture II

• Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan:
  A New Divide and Conquer Method for Achieving High Speed Division in Hardware. 535-540
  
• Tony Han, Sri Parameswaran:
  SWASAD: An ASIC Design for High Speed DNA Sequence Matching. 541-546
  
• Martin Palkovic, Miguel Miranda, Kristof Denolf, Peter Vos, Francky Catthoor:
  Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder. 547-552
  
• Debashis Panigrahi, Clark N. Taylor, Sujit Dey:
  A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. 553-
  

Layout III

• Qinwei Xu, Pinaki Mazumder:
  Efficient Macromodeling for On-Chip Interconnects. 561-566
  
• Silke Salewski, Erich Barke:
  An Upper Bound for 3D Slicing Floorplans. 567-572
  
• Jingcao Hu, Yangdong Deng, Radu Marculescu:
  System-Level Point-to-Point Communication Synthesis using Floorplanning Information. 573-579
  
• Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
  Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. 580-
  

Test I

• Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
  Multiple Faults: Modeling, Simulation and Test. 592-597
  
• Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik:
  Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. 598-603
  
• Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski:
  Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. 604-
  

Embedded Systems I

• Sornavalli Ramanathan, Rituparna Mandal:
  Low Power Solution for Wireless Applications. 615-618
  
• J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir:
  Address Code and Arithmetic Optimizations for Embedded Systems. 619-624
  
• Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo:
  Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications. 625-630
  
• N. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, J. Ramanujam, Alok N. Choudhary:
  Strategies for Improving Data Locality in Embedded Applications. 631-
  

Layout IV

• Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia:
  On Routing Demand and Congestion Estimation for FPGAs. 639-646
  
• Supratik Chakraborty, Rajeev Murgai:
  Layout-Driven Timing Optimization by Generalized De Morgan Transform. 647-654
  
• Rituparna Mandal, Dibyendu Goswami, Arup Dash:
  Reducing Library Development Cycle Time through an Optimum Layout Create Flow. 655-660
  
• Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho:
  A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. 661-
  

Test II

• Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das:
  Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. 671-676
  
• Irith Pomeranz, Sudhakar M. Reddy:
  A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. 677-682
  
• Makoto Sugihara, Hiroto Yasuura:
  Optimization of Test Accesses with a Combined BIST and External Test Scheme. 683-688
  
• Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri:
  Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). 689-
  

Embedded Systems II

• Dexin Li, Pai H. Chou, Nader Bagherzadeh:
  Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. 697-704
  
• Anupam Datta, Sidharth Choudhury, Anupam Basu:
  Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks. 705-710
  
• Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
  Input Space Adaptive Embedded Software Synthesis. 711-718
  
• Jiong Luo, Niraj K. Jha:
  Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. 719-
  

Verification II

• Malay K. Ganai, Adnan Aziz:
  Improved SAT-Based Bounded Reachability Analysis. 729-734
  
• Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti:
  Open Computation Tree Logic for Formal Verification of Modules. 735-740
  
• Raik Brinkmann, Rolf Drechsler:
  RTL-Datapath Verification using Integer Linear Programming. 741-746
  
• Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima:
  Verification of an Industrial CC-NUMA Server. 747-
  

Test III

• Sagar S. Sabade, D. M. H. Walker:
  Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. 755-760
  
• C. P. Ravikumar, Rahul Kumar:
  Divide-and-Conquer IDDQ Testing for Core-Based System Chips. 761-766
  
• Yun Shao, Irith Pomeranz, Sudhakar M. Reddy:
  Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. 767-772
  
• Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi:
  Test Solution for OTA Based Analog Circuits. 773-
  

Hot Chips from India

• Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji:
  Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. 781-788
  
• Sanjeev Patel:
  Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study. 789-794
  
• Ranjit Yashwante, Bhalchandra Jahagirdar:
  IEEE 1394a_2000 Physical Layer ASIC. 795-800
  
• T. Datta, C. S. Muralidharan:
  Definition, Design & Development of the IXE2424 Network Switch/Router ASIC. 801-802
  

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