"A Heuristic for Clock Selection in High-Level Synthesis."

J. Ramanujam et al. (2002)

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DOI: 10.1109/ASPDAC.2002.994956

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir:
A Heuristic for Clock Selection in High-Level Synthesis. ASP-DAC/VLSI Design 2002: 414-419

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