"An Architectural Level Energy Reduction Technique For Deep-Submicron Cache ..."

Tohru Ishihara, Kunihiro Asada (2002)

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DOI: 10.1109/ASPDAC.2002.994935

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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Tohru Ishihara, Kunihiro Asada:
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. ASP-DAC/VLSI Design 2002: 282-287

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