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ORCIDAjit Pal
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2010 – 2019
- 2016
[j15]Prasanta Majumdar, Ajit Pal, Tanmay De:
Extending light-trail into elastic optical networks for dynamic traffic grooming. Opt. Switch. Netw. 20: 1-15 (2016)- 2015
- [j14]Subhendu Barat, Ajit Pal, Tanmay De:
A load balanced approach of multicast routing and wavelength assignment in WDM networks. Int. J. Commun. Networks Distributed Syst. 15(1): 1-21 (2015) - [j13]Sumanta Pyne, Ajit Pal:
Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating. J. Low Power Electron. 11(1): 16-36 (2015) - [j12]Sumanta Pyne, Ajit Pal:
Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence. J. Low Power Electron. 11(2): 149-172 (2015) - 2014
- [c33]Sumanta Pyne, Ajit Pal:
Loop unrolling with fine grained power gating for runtime leakage power reduction. VDAT 2014: 1-6 - 2013
- [b1]Sudip Roy, Ajit Pal:
Impact of Leakage Power Reduction Techniques on Parametric Yield - Low-Power Design of Digital Integrated Circuits under Process Parameter Variations. LAP Lambert Academic Publishing 2013, ISBN 978-3-659-27391-9, pp. I-XVII, 1-131 - [j11]Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal:
An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis. J. Low Power Electron. 9(3): 350-362 (2013) - [j10]Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin Harer, Ansuman Banerjee, Subhankar Mukherjee:
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1801-1813 (2013) - [j9]Aritra Hazra, Sahil Goyal, Pallab Dasgupta, Ajit Pal:
Formal Verification of Architectural Power Intent. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 78-91 (2013) - [c32]Sumanta Pyne, Ajit Pal:
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence. VDAT 2013: 83-93 - [c31]Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Subhankar Mukherjee:
Formal Verification of Hardware / Software Power Management Strategies. VLSI Design 2013: 326-331 - [i1]Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal:
A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture. CoRR abs/1303.1645 (2013) - 2012
- [j8]Sumanta Pyne, Ajit Pal:
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques. J. Low Power Electron. 8(5): 604-623 (2012) - [c30]Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal:
Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture. ACITY (3) 2012: 633-648 - [c29]Rajdeep Mukherjee, Priyankar Ghosh, N. Sravan Kumar, Pallab Dasgupta, Ajit Pal:
Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework. ISED 2012: 267-271 - 2011
- [j7]Tanmay De, Puneet Jain, Ajit Pal:
Distributed dynamic grooming routing and wavelength assignment in WDM optical mesh networks. Photonic Netw. Commun. 21(2): 117-126 (2011) - [c28]Sukanta Bhattacharya, Tanmay De, Ajit Pal:
An Algorithm for Traffic Grooming in WDM Mesh Networks Using Dynamic Path Selection Strategy. ICDCN 2011: 263-268 - [c27]Mallikarjuna Rao Nimmagadda, Ajit Pal:
Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. ISVLSI 2011: 345-346 - 2010
- [j6]Sudip Roy, Ajit Pal:
A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation. J. Low Power Electron. 6(1): 80-92 (2010) - [j5]Tanmay De, Ajit Pal, Indranil Sengupta:
Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning. Photonic Netw. Commun. 20(2): 101-112 (2010) - [c26]Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha:
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. DAC 2010: 773-776 - [c25]Suman Paul, Subrata Nandi, Ajit Pal:
Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm. ICDCN 2010: 207-218 - [c24]Sukanta Bhattacharya, Tanmay De, Ajit Pal:
Traffic grooming in WDM mesh networks using dynamic path selection strategy. WOCN 2010: 1-5
2000 – 2009
- 2009
- [c23]Ajit Pal, Santanu Chattopadhyay:
Synthesis & Testing for Low Power. VLSI Design 2009: 37-38 - 2008
- [c22]Sudip Roy, Ajit Pal:
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? DSD 2008: 282-289 - [c21]Tanmay De, Ajit Pal, Indranil Sengupta:
Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning. ICDCN 2008: 452-463 - [c20]Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta:
A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing and Wavelength Assignment in Optical WDM Networks. ICIIS 2008: 1-6 - [c19]Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta:
A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks. ICON 2008: 1-6 - [c18]Sujan Kundu, Sudip Roy, Ajit Pal:
A power-aware wireless sensor network based bridge monitoring system. ICON 2008: 1-7 - 2007
- [c17]Akepati Sravan, Sujan Kundu, Ajit Pal:
Low Power Sensor Node for a Wireless Sensor Network. VLSI Design 2007: 445-450 - 2006
- [c16]Gopal Paul, Sambhu Nath Pradhan
, Ajit Pal, Bhargab B. Bhattacharya:
Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. APCCAS 2006: 1504-1507 - [c15]Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya:
On finding the minimum test set of a BDD-based circuit. ACM Great Lakes Symposium on VLSI 2006: 169-172 - 2005
- [e1]Ajit Pal, Ajay D. Kshemkalyani, Rajeev Kumar, Arobinda Gupta:
Distributed Computing - IWDC 2005, 7th International Workshop, Kharagpur, India, December 27-30, 2005, Proceedings. Lecture Notes in Computer Science 3741, Springer 2005, ISBN 3-540-30959-4 [contents] - 2004
- [c14]Ajit Pal, Umesh Patel:
Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks. IWDC 2004: 391-396 - [c13]Maitrali Marik, Ajit Pal:
Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. VLSI Design 2004: 73-78 - [c12]Debasis Samanta, Ajit Pal:
Synthesis of Low Power High Performance Dual-VT PTL Circuits. VLSI Design 2004: 85- - 2003
- [c11]Debasis Samanta, M. C. Dharmadeep, Ajit Pal:
Synthesis of high performance low power PTL circuits. ASP-DAC 2003: 209-212 - [c10]Debasis Samanta, Ajit Pal:
Synthesis of Dual-VT Dynamic CMOS Circuits. VLSI Design 2003: 303-308 - 2002
- [c9]Debasis Samanta, Nishant Sinha, Ajit Pal:
Synthesis of High Performance Low Power Dynamic CMOS Circuits. ASP-DAC/VLSI Design 2002: 99-104 - [c8]Debasis Samanta, Ajit Pal:
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. ASP-DAC/VLSI Design 2002: 193-198 - 2001
- [c7]Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal:
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. VLSI Design 2001: 227-
1990 – 1999
- 1999
- [c6]Sharath Kumar Kodase, N. V. Satyanarayana, Ajit Pal, Rajib Mall:
Deadline Assignment in Multiprocessor-Based Fault-Tolerant Systems. HiPC 1999: 158-162 - 1998
- [j4]Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal:
An algorithm for finding a non-trivial lower bound for channel routing1. Integr. 25(1): 71-84 (1998) - [j3]Anup K. Bhattacharjee, K. Ravindranath, Ajit Pal, Rajib Mall:
DDSCHED: A distributed dynamic real-time scheduling algorithm. Parallel Distributed Comput. Pract. 1(4) (1998) - 1997
- [c5]Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal:
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. VLSI Design 1997: 531-533 - 1996
- [j2]N. V. Satyanarayana, Rajib Mall, Ajit Pal:
A layered architecture for real-time systems. Microprocess. Microsystems 20(4): 241-250 (1996) - 1995
- [c4]Rajat Kumar Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal:
Computing area and wire length efficient routes for channels. VLSI Design 1995: 196-201 - [c3]Rajat Kumar Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal:
A general graph theoretic framework for multi-layer channel routing. VLSI Design 1995: 202-207 - 1993
- [c2]Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta:
NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. VLSI Design 1993: 80-83 - 1992
- [c1]Rajat Kumar Pal, Ajit Pal:
An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing. VLSI Design 1992: 259-262
1980 – 1989
- 1986
- [j1]Ajit Pal:
An Algorithm for Optimal Logic Design Using Multiplexers. IEEE Trans. Computers 35(8): 755-757 (1986)
Coauthor Index
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