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ORCIDYukiko Kubo
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2000 – 2009
- 2006
[j5]Yukiko Kubo, Atsushi Takahashi
:
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 725-733 (2006)- 2005
- [j4]Yukiko Kubo, Atsushi Takahashi:
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(5): 1283-1289 (2005) - [j3]Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design. Integr. 38(3): 439-449 (2005) - [c6]Yukiko Kubo, Atsushi Takahashi:
A global routing method for 2-layer ball grid array packages. ISPD 2005: 36-43 - 2004
- [c5]Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design. ACM Great Lakes Symposium on VLSI 2004: 220-223 - 2003
- [j2]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
An Incremental Wiring Algorithm for VLSI Layout Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5): 1203-1206 (2003) - 2002
- [j1]Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with hierarchical superconstraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 42-49 (2002) - [c4]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Chip size estimation based on wiring area. APCCAS (2) 2002: 113-118 - [c3]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. ASP-DAC/VLSI Design 2002: 467-472 - 2001
- [c2]Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with super hierarchical constraints. ISPD 2001: 144-149 - 2000
- [c1]Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92
Coauthor Index
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