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ORCIDCODES+ISSS 2013: Montreal, QC, Canada
- Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013, Montreal, QC, Canada, September 29 - October 4, 2013. IEEE 2013, ISBN 978-1-4799-1417-3
- Radu Marculescu
, Preeti Ranjan Panda:
Message from the program co-chairs. - Fazal Hameed, Lars Bauer, Jörg Henkel:
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache. 1:1-1:8 - Sven Goossens, Jasper Kuijsten, Benny Akesson, Kees Goossens:
A reconfigurable real-time SDRAM controller for mixed time-criticality systems. 2:1-2:10 - Chien-Chung Ho, Po-Chun Huang, Yuan-Hao Chang, Tei-Wei Kuo:
A DRAM-flash index for native flash file systems. 3:1-3:10 - Joël Porquet, Simha Sethumadhavan:
WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs. 4:1-4:9 - Francesco Conti, Andrea Marongiu, Luca Benini:
Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters. 5:1-5:10 - Aaron Severance, Guy G. F. Lemieux:
Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor. 6:1-6:10 - Renhai Chen, Yi Wang, Zili Shao:
DHeating: Dispersed heating repair for self-healing NAND flash memory. 7:1-7:10 - Da-Cheng Juan, Siddharth Garg, Jinpyo Park, Diana Marculescu:
Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling. 8:1-8:10 - Mengying Zhao, Hao Zhang, Xiang Chen, Yiran Chen, Chun Jason Xue:
Online OLED dynamic voltage scaling for video streaming applications on mobile devices. 9:1-9:10 - Wei Wang, Miodrag Bolic, Jonathan Parri:
pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment. 10:1-10:9 - Ke Bai, Jing Lu, Aviral Shrivastava, Bryce Holton:
CMSM: An efficient and effective Code Management for Software Managed Multicores. 11:1-11:9 - Nicola Bombieri, Franco Fummi, Sara Vinco:
On the automatic generation of GPU-oriented software applications from RTL IPs. 12:1-12:10 - Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Jürgen Teich:
Run-time adaption for highly-complex multi-core systems. 13:1-13:8 - Mingsong Chen, Lei Zhou, Geguang Pu, Jifeng He:
Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis. 14:1-14:10 - Wei Zuo, Peng Li, Deming Chen, Louis-Noël Pouchet, Shunan Zhong, Jason Cong:
Improving polyhedral code generation for high-level synthesis. 15:1-15:10 - Shuo Li, Nasim Farahini, Ahmed Hemani, Kathrin Rosvall, Ingo Sander:
System level synthesis of hardware for DSP applications using pre-characterized function implementations. 16:1-16:10 - Mahboobeh Ghorbani, Paul Bogdan:
A cyber-physical system approach to artificial pancreas design. 17:1-17:10 - Joseph Tarango, Eamonn J. Keogh, Philip Brisk:
Instruction set extensions for Dynamic Time Warping. 18:1-18:10 - Jean-Philippe Diguet, Marius Strum, Nicolas Le Griguer, Lydie Caetano, Martha Johanna Sepúlveda:
Scalable NoC-based architecture of neural coding for new efficient associative memories. 19:1-19:9 - Kristofor D. Carlson, Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar:
Design space exploration and parameter tuning for neuromorphic applications. 20:1-20:2 - Olivier Temam:
Hardware neural network accelerators. 21:1 - Kevin M. Irick:
Embedded neuromorphic vision systems. 22:1 - Beiye Liu, Miao Hu, Hai Li, Yiran Chen, Chun Xue:
Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems. 23:1 - Sebastian Graf, Michael Glaß, Dominic Wintermann, Jürgen Teich, Christoph Lauer:
IVaM: Implicit variant modeling and management for automotive embedded systems. 24:1-24:10 - Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Jan R. Seyler:
Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet. 25:1-25:10 - Wanli Chang, Martin Lukasiewycz, Sebastian Steinhorst, Samarjit Chakraborty:
Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization. 26:1-26:10 - Lucas Francisco Wanner, Salma Elmalaki, Liangzhen Lai, Puneet Gupta, Mani B. Srivastava:
VarEMU: An emulation testbed for variability-aware software. 27:1-27:10 - Michele Bertasi, Giuseppe Di Guglielmo, Graziano Pravadelli:
Automatic generation of compact formal properties for effective error detection. 28:1-28:10 - Laurence Pierre, Zeineb Bel Hadj Amor:
Automatic refinement of requirements for verification throughout the SoC design flow. 29:1-29:10 - Majid Namaki-Shoushtari, Abbas Rahimi, Nikil D. Dutt, Puneet Gupta, Rajesh K. Gupta:
ARGO: Aging-aware GPGPU register file allocation. 30:1-30:9 - Yue Gao, Yanzhi Wang, Sandeep K. Gupta, Massoud Pedram:
An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems. 31:1-31:10 - Di Zhu, Siyu Yue, Yanzhi Wang, Younghyun Kim, Naehyuck Chang, Massoud Pedram:
Designing a residential hybrid electrical energy storage system based on the energy buffering strategy. 32:1-32:9 - Lide Zhang, David R. Bild, Robert P. Dick, Zhuoqing Morley Mao, Peter A. Dinda:
Panappticon: Event-based tracing to measure mobile application and platform performance. 33:1-33:10 - Moritz Neukirchner, Kai Lampka, Sophie Quinton, Rolf Ernst:
Multi-mode monitoring for mixed-criticality real-time systems. 34:1-34:10 - Abbas Rahimi, Andrea Marongiu, Rajesh K. Gupta, Luca Benini:
A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters. 35:1-35:10 - Suhas Chakravarty, Zhuoran Zhao, Andreas Gerstlauer:
Automated, retargetable back-annotation for host compiled performance and power modeling. 36:1-36:10
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