"Verification and Synthesis of Clock-Gated Circuits."

Yu-Yun Dai, Robert K. Brayton (2019)

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DOI: 10.1109/TCAD.2018.2808231

access: closed

type: Journal Article

metadata version: 2020-09-24

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Yu-Yun Dai, Robert K. Brayton:
Verification and Synthesis of Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 366-379 (2019)

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