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ORCIDMahmoud Zangeneh
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2010 – 2019
- 2016
[j2]Mahmoud Zangeneh, Ajay Joshi:
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 884-896 (2016)- 2015
- [c7]Boyou Zhou
, Ronen Adato, Mahmoud Zangeneh, Tianyu Yang, Aydan Uyar, Bennett B. Goldberg, M. Selim Ünlü, Ajay Joshi:
Detecting hardware trojans using backside optical imaging of embedded watermarks. DAC 2015: 111:1-111:6 - [c6]T. Berkin Cilingiroglu, Mahmoud Zangeneh, Aydan Uyar, W. Clem Karl, Janusz Konrad, Ajay Joshi, Bennett B. Goldberg, M. Selim Ünlü:
Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits. DATE 2015: 597-600 - 2014
- [j1]Mahmoud Zangeneh, Ajay Joshi:
Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1815-1828 (2014) - [c5]Mahmoud Zangeneh, Ajay Joshi:
Sub-threshold logic circuit design using feedback equalization. DATE 2014: 1-6 - 2012
- [c4]Mahmoud Zangeneh, Ajay Joshi:
Performance and energy models for memristor-based 1T1R RRAM cell. ACM Great Lakes Symposium on VLSI 2012: 9-14 - 2010
- [c3]Hossein Aghababa, Mahmoud Zangeneh, Ali Afzali-Kusha, Behjat Forouzandeh:
Statistical delay modeling of read operation of SRAMs due to channel length variation. ISCAS 2010: 2502-2505
2000 – 2009
- 2009
- [c2]Mahmoud Zangeneh, Nasser Masoumi:
An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies. ECCTD 2009: 470-475 - [c1]Mahmoud Zangeneh, Hossein Aghababa, Behjat Forouzandeh:
Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation. ECCTD 2009: 493-498
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