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Bojan Maric
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2020 – today
- 2021
- [c5]David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau:
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. HCS 2021: 1-23
2010 – 2019
- 2014
- [b1]Bojan Maric:
Cache designs for reliable hybrid high and ultra-low voltage operation. Polytechnic University of Catalonia, Spain, 2014 - [j2]Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation. ACM Trans. Design Autom. Electr. Syst. 20(1): 10:1-10:25 (2014) - [j1]Bojan Maric, Jaume Abella, Mateo Valero:
Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2211-2215 (2014) - 2013
- [c4]Bojan Maric, Jaume Abella, Mateo Valero:
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation. DAC 2013: 84:1-84:8 - [c3]Bojan Maric, Jaume Abella, Mateo Valero:
Efficient cache architectures for reliable hybrid voltage operation using EDC codes. DATE 2013: 917-920 - 2012
- [c2]Bojan Maric, Jaume Abella, Mateo Valero:
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. ACM Great Lakes Symposium on VLSI 2012: 245-250 - 2011
- [c1]Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid high-performance low-power and ultra-low energy reliable caches. Conf. Computing Frontiers 2011: 12
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