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"Simultaneous block and I/O buffer floorplanning for flip-chip design."

Chih-Yang Peng et al. (2006)

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DOI: 10.1109/ASPDAC.2006.1594684

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/aspdac/PengCCW06
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  persistent URL:
  - https://dblp.org/rec/conf/aspdac/PengCCW06
Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang:
Simultaneous block and I/O buffer floorplanning for flip-chip design. ASP-DAC 2006: 213-218

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