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ORCIDSachin Shrivastava
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2010 – 2019
- 2012
[c11]Sachin Shrivastava, Harindranath Parameswaran:
Efficient reduction techniques for statistical model generation of standard cells. ISQED 2012: 358-363- 2011
- [c10]Sachin Shrivastava, Harindranath Parameswaran:
Improved Timing Windows Overlap Check Using Statistical Timing Analysis. VLSI Design 2011: 70-75
2000 – 2009
- 2008
- [c9]Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava:
Computation of Waveform Sensitivity Using Geometric Transforms for SSTA. ISQED 2008: 373-378 - [c8]Sachin Shrivastava, Harindranath Parameswaran:
Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping. ISQED 2008: 445-449 - 2007
- [c7]Ratnakar Goyal, Sachin Shrivastava, Harindranath Parameswaran, Parveen Khurana:
Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation. VLSI Design 2007: 278-282 - 2006
- [c6]Sachin Shrivastava, Harindranath Parameswaran, Rajendra Pratap:
Design Partitioning for Reducing Crosstalk Analysis Time. APCCAS 2006: 796-800 - [c5]Ravi Arora, Sachin Shrivastava:
Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint! APCCAS 2006: 805-807 - [c4]Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma:
Crosstalk analysis using reconvergence correlation. ASP-DAC 2006: 79-83 - 2005
- [c3]Sachin Shrivastava, Sreeram Chandrasekar:
Crosstalk Noise Analysis at Multiple Frequencies. VLSI Design 2005: 342-347 - 2004
- [c2]Sachin Shrivastava, Dhanoop Varghese, Vikas Narang, N. V. Arvind:
Improved Approach for Noise Propagation to Identify Functional Noise Violations. VLSI Design 2004: 705-708 - [c1]Sreeram Chandrasekar, Sachin Shrivastava, Ajoy Mandal, Sornavalli Ramanathan:
An Efficient Approach to Crosstalk Noise Analysis at Multiple Operating Modes. VLSI Design 2004: 709-712
Coauthor Index
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