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ORCIDKazumi Hatayama
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2020 – today
- 2023
[j11]Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi:
Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. IEICE Electron. Express 20(1): 20220470 (2023)- [c45]Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi:
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. ITC 2023: 47-55 - [c44]Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. ITC-Asia 2023: 1-6 - 2022
- [j10]Yujie Zhao
, Kentaroh Katoh, Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. J. Electron. Test. 38(1): 21-38 (2022) - [c43]Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. ATS 2022: 37-42 - [c42]Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS 2022: 1 - 2021
- [c41]Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
High Precision Measurement of Sub-Nano Ampere Current in ATE Environment. ATS 2021: 139-140 - [c40]Gaku Ogihara, Takayuki Nakatani, Daisuke Iimori, Shogo Katayama, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Jianglin Wei, Kazumi Hatayama, Haruo Kobayashi:
Evaluation of High-Precision Nano-Ampere Current Measurement Method for Mass Production. ICECS 2021: 1-6 - [c39]Shuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, Minh Tri Tran, Shogo Katayama, Kazumi Hatayama, Haruo Kobayashi:
Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method. IOLTS 2021: 1-6 - [c38]Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies. ITC 2021: 284-288 - [c37]Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi:
Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer. ITC 2021: 364-373 - 2020
- [c36]Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, Kazumi Hatayama, Haruo Kobayashi:
Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers. ATS 2020: 1-6 - [c35]Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Accurate Testing of Precision Voltage Reference by DC-AC Conversion. ATS 2020: 1-2 - [c34]Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama:
Innovative Test Practices in Asia. VTS 2020: 1
2010 – 2019
- 2019
- [c33]Riho Aoki, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Yuto Sasaki, Kosuke Machida, Takayuki Nakatani, Jianlong Wang, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Evaluation of Null Method for Operational Amplifier Short-Time Testing. ASICON 2019: 1-4 - [c32]Jiang-Lin Wei, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Nene Kushita, Takahiro Arai, Lei Sha, Anna Kuwana, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato:
High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm. ASICON 2019: 1-4 - [c31]Yuto Sasaki, Kosuke Machida, Riho Aoki, Shogo Katayama, Takayuki Nakatani, Jianlong Wang, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion. ITC-Asia 2019: 1-6 - [c30]Yusuke Asada, Takahiko Shimizu, Yuji Gendai, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jiang-Lin Wei, Nene Kushita, Hirotaka Arai, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi:
Innovative Test Practices in Japan. VTS 2019: 1 - 2018
- [c29]Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama:
Innovative practices on test in Japan. VTS 2018: 1 - 2017
- [c28]Kazumi Hatayama, Masahiro Ishida:
Innovative practices session 9B innovative practices in Asia-1: From quality perspective. VTS 2017: 1 - [c27]Kazumi Hatayama, Masahiro Ishida:
Innovative practices session 10B innovative practices in Asia-2: From cost perspective. VTS 2017: 1 - 2016
- [j9]Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato:
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. 32(5): 601-609 (2016) - 2014
- [j8]Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato:
A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1056-1066 (2014) - [c26]Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS 2014: 292-297 - [c25]Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue:
Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA 2014: 85-88 - 2013
- [c24]Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia:
Special session 4B: Elevator talks. VTS 2013: 1 - 2012
- [c23]Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10 - [c22]Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC 2012: 1-8 - 2011
- [j7]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. 94-D(6): 1216-1226 (2011) - 2010
- [j6]Kazumi Hatayama, Tsuyoshi Shinogi:
Foreword. IEICE Trans. Inf. Syst. 93-D(1): 1 (2010) - [j5]Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1309-1318 (2010) - [c21]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Scan based process parameter estimation through path-delay inequalities. ISCAS 2010: 3553-3556 - [c20]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Path clustering for adaptive test. VTS 2010: 15-20
2000 – 2009
- 2009
- [c19]Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu:
An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium 2009: 151-156 - [c18]Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara:
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD 2009: 97-104 - [c17]Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo:
Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS 2009: 27-32 - 2008
- [j4]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of Delay Test Quality and Its Application to Test Generation. Inf. Media Technol. 3(4): 717-728 (2008) - [j3]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of Delay Test Quality and Its Application to Test Generation. IPSJ Trans. Syst. LSI Des. Methodol. 1: 104-115 (2008) - [c16]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS 2008: 55-60 - [c15]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58 - 2007
- [c14]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417 - 2006
- [c13]Kazumi Hatayama:
Session Abstract. VTS 2006: 200-201 - 2004
- [c12]Kazumi Hatayama, Rochit Rajsuman:
Opportunities with the open architecture test system. ASP-DAC 2004: 334 - 2003
- [j2]Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Kazumi Hatayama, Kazuyuki Nomoto:
DFT Timing Design Methodology for Logic BIST. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3049-3055 (2003) - [c11]Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto:
DFT timing design methodology for at-speed BIST. ASP-DAC 2003: 763-768 - 2002
- [c10]Kazumi Hatayama, Michinobu Nakao, Yasuo Sato:
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297 - [c9]Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo:
Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012 - 2001
- [c8]Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo:
Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244-
1990 – 1999
- 1999
- [c7]Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada:
Low overhead test point insertion for scan-based BIST. ITC 1999: 348-357 - 1997
- [c6]Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto:
Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium 1997: 112-115 - [c5]Michinobu Nakao, Kazumi Hatayama, Isao Higashi:
Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium 1997: 359- - [c4]Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada:
A practical approach to instruction-based test generation for functional modules of VLSI processors. VTS 1997: 17-23 - 1995
- [c3]Hiroshi Date, Michinobu Nakao, Kazumi Hatayama:
A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium 1995: 252-258 - 1993
- [j1]Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi:
Sequential circuit test generation by real number simulation. Syst. Comput. Jpn. 24(9): 64-75 (1993) - 1992
- [c2]Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi:
Sequential Test Generation Based on Real-Value Logic. ITC 1992: 41-48
1980 – 1989
- 1989
- [c1]Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama:
Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC 1989: 161-165
Coauthor Index
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