Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999.
IEEE Computer Society 1999
Atlantic City, NJ, USA
Session 2: Mcm and Known-Good-Die Testing
Session 3: Dynamic Current Testing
Session 4: Low Power And Diagnosis In Bist
Session 5: Volume Production Testing
Session 6: Microprocessor Testing
Session 7: Board Test - Lecture Series
Adam W. Ley
: The integration of boundary-scan test methods to a mixed-signal environment.
Session 8: Delay Testing
Session 9: Analog Test Methods
Session 10: Virtual And Real Test Software
J. J. O. Riordan
: Design of a test simulation environment for test program development.
Session 11: DFT
Session 12: Embedded Memories
: Practical scan test generation and application for embedded FIFOs.
Dilip K. Bhavsar
: An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264.
Session 13: Mems Fault Modeling and Test
Session 14: Industrial Applications of BIST
Session 15: Production Wafer Test: Where the Probes Meet the Pads
Dean A. Gahagan
: RF (gigahertz) ATE production testing on wafer: options and tradeoffs.
Session 16: Design Validation and Analysis for Evolving Technologies
Session 17: Board Test: Interconnect Test
Session 18: Enhanced Test and Diagnosis of IC Process Defects
Session 19: Embedded Core Test
: Testing a system-on-a-chip with embedded microprocessor.
Session 20: Issues in Tester Accuracy
Session 21: Mixed Signal BIST Techniques
Session 22: Board Test: Practice Makes Perfect
Session 23: Fault Simulation from Bridges to RTL
Session 24: Practicing Embedded Core Test
Session 25: (Panel) Is Analog Fault Simulation a Key to Product Quality? Practical Considerations
: Analog Fault Simulation: Key to Product Quality, or a Foot in the Door.
: Closing The Gap Between Process Development and Mixed Signal Design and Testing.
Session 26: On-Line Testing Techniques
Session 27: System Test - Lecture Series
: System design verification tests - an overview.
: PC manufacturing test in a high volume environment.
Session 28: Production I - Testing Beyond Single-Threshold Measurements
Testing Analog to Digital Converters
: Linearity testing issues of analog to digital converters.
: Testing high speed high accuracy analog to digital converters embedded in systems on a chip.
, Haydar Bilhan
: Relating linearity test results to design flaws of pipelined analog to digital converters.
Issues in High-Speed Testing
Burnell G. West
: Accuracy requirements in at-speed functional test.
David C. Keezer
, Q. Zhou
: Test support processors for enhanced testability of high performance circuits.
Test Methodology State of Practice and Case Studies
, Magdy S. Abadir
: Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.
Kenneth M. Butler
: A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data.
System Test Methods from DFT to End of Live
: Robust test methods applied to functional design verification.
, Michael S. Hsiao
: An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques.
Design for Diagnostics
Mixed-Signal ATE Issues and Optical Probing
: Flexible ATE module with reconfigurable circuit and its application [to CMOS imager test].
On-Line Testing for FPGAS and Processors
Advanced Solution for SOC Test
Applying Diagnosis in a Production Test Environment
Time-to-Market - Lecture Series
: Design for test and time to market-friends or foes.
Bulent I. Dervisoglu
: Design for testability: it is time to deliver it for Time-to-Market.
High Time for High-Level ATPG
: High level ATPG is important and is on its way!
: SIA Roadmaps: Sunset Boulevard for l_DDQ.
Thin Gate Oxide Reliability
Panel 6: ITC'99 Benchmark Circuits - Preliminary Results
Sudhakar M. Reddy
: Application of Tools Developed at the University of Iowa to ITC Benchmarks.
Increasing Test Coverage in VLSI Design
Jacob A. Abraham
: Position Statement: Increasing Test Coverage in a VLSI Design Course.
: Increasing test coverage in a VLSI design course.
: Panel Statement: Increasing test coverage in a VLSI design course.
: Position Statement: Testing in a VLSI Design Course.
Frans de Jong
: SCITT: Back to Basics in Mass Production Testing.
Back to Basics in Mass Production Testing
: Static Component Interconnection Test Technology (SCITT).
David M. Wu
: DFT is all I can afford, who cares about Design for Yield or Design for Reliability!
DIFT is all I Can Afford, Who Vares About Design for Yield or Design for Reliability!
D. M. H. Walker
: Design for Yield and Reliability is MORE Important Than DFT.
David M. Wu
: "DFY and DFR are more important than DFT".
Output in STIL, Input in STIL
: STIL: the device-oriented database for the test development lifecycle.
Brion L. Keller
: Using STIL to describe embedded core test requirements.
ITC'98 Best Paper