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Thomas Röwer

Thomas Roewer

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This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.

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2020 – today

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2024
[c7]
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Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang:
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC 2024: 254-256

2010 – 2019

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2018
[c6]
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Mohammad Alian, Seungwon Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang, Thomas Roewer, Adam J. McPadden, Oliver O'Halloran, Deming Chen, Jinjun Xiong, Daehoon Kim, Wen-Mei W. Hwu, Nam Sung Kim:
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network. MICRO 2018: 802-814
2017
[c5]
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Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad:
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. MICRO 2017: 15-26
2012
[c4]
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Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno:
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. FPGA 2012: 153-162

2000 – 2009

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2001
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Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Design and Verification of a Stack Processor Virtual Component. IEEE Micro 21(2): 69-80 (2001)
2000
[b1]
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Thomas Röwer:
Programmable intellectual property modules for system design by reuse. ETH Zurich, Zürich, Switzerland, 2000
[c3]
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Thomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A new paradigm for very flexible SONET/SDH IP-modules. CICC 2000: 533-536

1990 – 1999

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1999
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Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann:
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. ITC 1999: 414-420
1998
[c1]
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Manfred Stadler, Markus Thalmann, Thomas Röwer, Norbert Felber, Wolfgang Fichtner:
An embedded stack microprocessor for SDH telecommunication applications. CICC 1998: 17-20

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