32. DAC 1995: San Francisco, California, USA

Design of UltraSPARC

• Marc Tremblay, Guillermo Maturana, Atsushi Inoue, Leslie Kohn:
  A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I. 2-6
  
• Lawrence Yang, David Gao, Jamshid Mostoufi, Raju Joshi, Paul Loewenstein:
  System Design Methodology of UltraSPARC-I. 7-12
  
• James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong:
  UltraSPARC-I Emulation. 13-18
  
• A. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan, Manjunath Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, S. Simovich, R. Sunder, B. Sur, W. Vercruysse, Michelle Wong, P. Yip, Robert K. Yu, J. Zhou, Gregory B. Zyner:
  CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc. 19-22
  

Power Considerations in Synthesis

• Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino:
  Computing the Maximum Power Cycles of a Sequential Circuit. 23-28
  
• Jui-Ming Chang, Massoud Pedram:
  Register Allocation and Binding for Low Power. 29-35
  
• Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh:
  Memory Segmentation to Exploit Sleep Mode Operation. 36-41
  
• Raul San Martin, John P. Knight:
  Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level. 42-47
  

Technology and Layout Dependent Synthesis

• Kuo-Hua Wang, TingTing Hwang:
  Boolean Matching for Incompletely Specified Functions. 48-53
  
• Bernd Wurth, Klaus Eckl, Kurt Antreich:
  Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm. 54-59
  
• Ted Stanion, Carl Sechen:
  A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. 60-64
  
• Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao:
  Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. 65-69
  
• Hirendu Vaishnav, Massoud Pedram:
  Minimizing the Routing Cost During Logic Extraction. 70-75
  

Issues in EDA Frameworks

• Stephen T. Frezza, Steven P. Levitan, Panos K. Chrysanthis:
  Requirements-Based Design Evaluation. 76-81
  
• Eric W. Johnson, Jay B. Brockman:
  Incorporating Design Schedule Management into a Flow Management System. 82-87
  
• Joachim Altmeyer, Bernd Schürmann, Martin Schütze:
  Generating ECAD Framework Code from Abstract Models. 88-93
  
• Ansgar Bredenfeld, Raul Camposano:
  Tool Integration and Construction Using Generated Graph-Based Design Representations. 94-99
  

Panel: Managing Design Process Change - Lessons Learned

Scheduling and Retiming in Architectural Synthesis

• Tai Ly, David Knapp, Ron Miller, Don MacMillen:
  Scheduling Using Behavioral Templates. 101-106
  
• Miodrag Potkonjak, Mani B. Srivastava:
  Rephasing: A Transformation Technique for the Manipulation of Timing Constraints. 107-112
  
• Y. G. DeCastelo-Vide-e-Souza, Miodrag Potkonjak, Alice C. Parker:
  Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming. 113-118
  

Delay Test and Diagnosis

• Uwe Sparmann, D. Luxenburger, Kwang-Ting Cheng, Sudhakar M. Reddy:
  Fast Identification of Robust Dependent Path Delay Faults. 119-125
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On Synthesis-for-Testability of Combinational Logic Circuits. 126-132
  
• Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel:
  Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. 133-138
  

Discrete-Event Simulation

• Roger D. Chamberlain:
  Parallel Logic Simulation of VLSI Systems. 139-143
  
• Peter A. Walker, Sumit Ghosh:
  Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors. 144-150
  
• Robert S. French, Monica S. Lam, Jeremy R. Levitt, Kunle Olukotun:
  A General Method for Compiling Event-Driven Simulations. 151-156
  

Panel: Power Minimization in IC Design

Storage Synthesis and Optimization

• Wei-Kai Cheng, Youn-Long Lin:
  A Transformation-Based Approach for Storage Optimization. 158-163
  
• Tsung-Yi Wu, Youn-Long Lin:
  Register Minimization beyond Sharing among Variables. 164-169
  
• Elof Frank, Salil Raje, Majid Sarrafzadeh:
  Constrained Register Allocation in Bus Architectures. 170-175
  

Retiming and Sequential ATPG

• Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly:
  On Test Set Preservation of Retimed Circuits. 176-182
  
• Elizabeth M. Rudnick, Janak H. Patel:
  Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. 183-188
  
• Peichen Pan, C. L. Liu:
  Partial Scan with Pre-selected Scan Signals. 189-194
  

Partitioning and Placement

• Charles J. Alpert, So-Zen Yao:
  Spectral Partitioning: The More Eigenvectors, The Better. 195-200
  
• Prashant Sawkar, Donald E. Thomas:
  Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. 201-205
  
• Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu: Performance-Driven Partitioning Using a Replication Graph Approach. 206-210
• William Swartz, Carl Sechen:
  Timing Driven Placement for Large Standard Cell Circuits. 211-215
  
• Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng:
  Quantified Suboptimality of VLSI Layout Heuristics. 216-221
  

Design Case Studies

• Thomas W. Albrecht:
  Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation. 222-227
  
• Peter Zepter, Thorsten Grötker, Heinrich Meyr:
  Digital Receiver Design Using VHDL Generation from Data Flow Graphs. 228-233
  
• Charles H. Malley, Max Dieudonné:
  Logic Verification Methodology for PowerPC Microprocessors. 234-240
  

Panel: University-Industry Ties: How Can They Be Improved?

Low Power Design

• Srinivas Devadas, Sharad Malik:
  A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. 242-247
  
• Sasan Iman, Massoud Pedram:
  Logic Extraction and Factorization for Low Power. 248-253
  
• Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli:
  Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool. 254-260
  

Extraction and Module Generation

• Ajay Chandna, C. David Kibler, Richard B. Brown, Mark Roberts, Karem A. Sakallah:
  The Aurora RAM Compiler. 261-266
  
• Sanjay Rekhi, J. Donald Trotter, Daniel H. Linder:
  Automatic Layout Synthesis of Leaf Cells. 267-272
  
• N. P. van der Meijs, Arjan J. van Genderen:
  Delayed Frontal Solution for Finite-Element Based Resistance Extraction. 273-278
  

Advanced Methods in Practice

• Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek:
  Test Program Generation for Functional Verification of PowerPC Processors in IBM. 279-285
  
• David Knapp, Tai Ly, Don MacMillen, Ron Miller:
  Behavioral Synthesis Methodology for HDL-Based Specification and Validation. 286-291
  
• Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza:
  Design-Flow and Synthesis for ASICs: A Case Study. 292-297
  
• Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl:
  Model Checking in Industrial Hardware Design. 298-303
  

Sequential Logic Synthesis

• Kumar N. Lalgudi, Marios C. Papaefthymiou:
  DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. 304-309
  
• Rahul B. Deokar, Sachin S. Sapatnekar:
  A Fresh Look at Retiming Via Clock Skew Optimization. 310-315
  
• Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton:
  The Validity of Retiming Sequential Circuits. 316-321
  
• Ireneusz Karkowski, Ralph H. J. M. Otten:
  Retiming Synchronous Circuitry with Imprecise Delays. 322-326
  
• Shihming Liu, Massoud Pedram, Alvin M. Despain:
  A Fast State Assignment Procedure for Large FSMs. 327-332
  

Fault Modeling and Simulation

• Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
  Software Accelerated Functional Fault Simulation for Data-Path Architectures. 333-338
  
• Rolf Krieger, Bernd Becker, Martin Keim:
  Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy. 339-344
  
• Haluk Konuk, F. Joel Ferguson, Tracy Larrabee:
  Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. 345-351
  
• Lluis Ribas, Jordi Carrabina:
  Analysis of Switch-Level Faults by Symbolic Simulation. 352-357
  

CAD for Interconnect

• Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi:
  Transmission Line Synthesis. 358-363
  
• Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi:
  The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. 364-369
  
• Vasant B. Rao:
  Delay Analysis of the Distributed RC Line. 370-375
  
• Luis Miguel Silveira, Mattan Kamon, Jacob White:
  Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures. 376-380
  
• Sharad Mehrotra, Paul D. Franzon, Michael B. Steer:
  Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs. 381-387
  

Tutorial: ASIC Prototyping

Datapath Synthesis and Modeling

• Chuck Monahan, Forrest Brewer:
  Symbolic Modeling and Evaluation of Data Paths. 389-394
  
• Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
  Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. 395-401
  
• Donald S. Gelosh, Dorothy E. Setliff:
  Deriving Efficient Area and Delay Estimates by Modeling Layout Tools. 402-407
  

Learning and Counterexamples in Formal Verification

• Jochen Bern, Christoph Meinel, Anna Slobodová:
  Efficient OBDD-Based Boolean Manipulation in CAD beyond Current Limits. 408-413
  
• Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan: Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. 414-419
• Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita:
  Advanced Verification Techniques Based on Learning. 420-426
  
• Edmund M. Clarke, Orna Grumberg, Kenneth L. McMillan, Xudong Zhao:
  Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking. 427-432
  

Analog CAD

• Wim Kruiskamp, Domine Leenaerts:
  DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm. 433-438
  
• Ivan L. Wemple, Andrew T. Yang:
  Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels. 439-444
  
• Koen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen:
  Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits. 445-449
  
• Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman:
  System-Level Design for Test of Fully Differential Analog Circuits. 450-454
  

Panel: DOS, Windows, UNIX: EDA and the O.S. War

Software Analysis and Synthesis

• Yau-Tsun Steven Li, Sharad Malik:
  Performance Analysis of Embedded Software Using Implicit Path Enumeration. 456-461
  
• Pai H. Chou, Gaetano Borriello:
  Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems. 462-467
  
• Sanjiv Narayan, Daniel Gajski:
  Interfacing Incompatible Protocols Using Interface Process Generation. 468-473
  

Electrical Simulation

• Peter Feldmann, Roland W. Freund:
  Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm. 474-479
  
• Ricardo Telichevesky, Kenneth S. Kundert, Jacob White:
  Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods. 480-484
  
• Mike Chou, Tom Korsmeyer, Jacob White:
  Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach. 485-490
  

Optimization of Clock and Power Distribution

• Joe G. Xi, Wayne Wei-Ming Dai:
  Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution. 491-496
  
• Ashok Vittal, Malgorzata Marek-Sadowska:
  Power Optimal Buffered Clock Tree Design. 497-502
  
• Ashok Vittal, Malgorzata Marek-Sadowska:
  Power Distribution Topology Design. 503-507
  
• Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao:
  On the Bounded-Skew Clock and Steiner Routing Problems. 508-513
  

Concurrent Engineering

• Asim Smailagic, Daniel P. Siewiorek, Drew Anderson, Chris Kasabach, Thomas L. Martin, John Stivoric:
  Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems. 514-519
  
• Giovanni Mancini, Dave Yurach, Spiros Boucouris:
  A Methodology for HW-SW Codesign in ATM. 520-527
  
• Allan Silburt, Ian Perryman, Janick Bergeron, Stacy Nichols, Mario Dufresne, Greg Ward:
  Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation. 528-533
  

Panel: The ESDA Landscape: Who Will Dominate?

Formal Verification of Arithmetic Circuits

• Randal E. Bryant, Yirng-An Chen:
  Verification of Arithmetic Circuits with Binary Moment Diagrams. 535-541
  
• Shinji Kimura:
  Residue BDD and Its Application to the Verification of Arithmetic Circuits. 542-545
  
• Zheng Zhou, Wayne Burleson:
  Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions. 546-551
  

Routing for FPGAs

• Wai-Kei Mak, D. F. Wong:
  On Optimal Board-Level Routing for FPGA-Based Logic Emulation. 552-556
  
• Yuh-Sheng Lee, Allen C.-H. Wu:
  A Performance and Routability Driven Router for FPGAs Considering Path Delays. 557-561
  
• Michael J. Alexander, Gabriel Robins:
  New Performance-Driven FPGA Routing Algorithms. 562-567
  
• Yu-Liang Wu, Malgorzata Marek-Sadowska:
  Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. 568-573
  
• Steven Trimberger:
  Effects of FPGA Architecture on FPGA Routing. 574-578
  

EDA and the WWW

• Mário J. Silva, Randy H. Katz:
  The Case for Design Using the World Wide Web. 579-585
  

Panel: The Impact of the World Wide Web on Electronic Design and EDA

Code Generation for Embedded Systems

• Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich:
  Synthesis of Software Programs for Embedded Control Applications. 587-592
  
• Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess:
  Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. 593-598
  
• Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang:
  Code Optimization Techniques for Embedded DSP Microprocessors. 599-604
  
• Ulrich Bieker, Peter Marwedel:
  Retargetable Self-Test Program Generation Using Constraint Logic Programming. 605-611
  

Switching Activity and Power Analysis

• Farid N. Najm:
  Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits. 612-617
  
• Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
  Accurate Estimation of Combinational Circuit Activity. 618-622
  
• Farid N. Najm, Michael Y. Zhang:
  Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits. 623-627
  
• Radu Marculescu, Diana Marculescu, Massoud Pedram:
  Efficient Power Estimation for Highly Correlated Input Streams. 628-634
  
• Farid N. Najm, Shashank Goel, Ibrahim N. Hajj:
  Power Estimation in Sequential Circuits. 635-640
  

Combinational Logic Synthesis

• Olivier Coudert, Jean Christophe Madre:
  New Ideas for Solving Covering Problems. 641-646
  
• Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
  Logic Synthesis for Engineering Change. 647-652
  
• Yuichi Nakamura, Takeshi Yoshimura:
  A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix. 653-657
  
• Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita:
  Multi-Level Logic Minimization Based on Multi-Signal Implications. 658-662
  
• Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
  An Efficient Algorithm for Local Don't Care Sets Calculation. 663-667
  
• Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich:
  Logic Clause Analysis for Delay Optimization. 668-672
  

Panel: Deep Submicron Design Challenges

Complexity Measures for VHDL

• Reinaldo A. Bergamaschi:
  Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? 674-677
  
• Cristian A. Giumale, Hilary J. Kahn:
  Information Models of VHDL. 678-683
  
• Neal S. Stollon, John D. Provence:
  Measures of Syntactic Complexity for Modeling Behavioral VHDL. 684-689
  

Timing Analysis and Optimization

• Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi:
  Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. 690-695
  
• Jin-fuw Lee, Donald T. Tang:
  An Algorithm for Incremental Timing Analysis. 696-701
  
• Alessandro Dal Fabbro, Bruno Franzini, Luigi Croce, Carlo Guardiani:
  An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells. 702-706
  
• Samir Jain, Randal E. Bryant, Alok Jain:
  Automatic Clock Abstraction from Sequential Circuits. 707-711
  

Asynchronous Synthesis

• Bill Lin, Gjalt G. de Jong, Tilman Kolks:
  Hierarchical Optimization of Asynchronous Circuits. 712-717
  
• Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin:
  Externally Hazard-Free Implementations of Asynchronous Circuits. 718-724
  
• Peter Vanbekbergen, Albert Wang, Kurt Keutzer:
  A Design and Validation System for Asynchronous Circuits. 725-730
  

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