32. DAC 1995:
San Francisco, California, USA Bryan Preas (Ed.):
Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995.
ACM Press 1995, ISBN 0-89791-725-1 Design of UltraSPARC
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/dac/GateleyBCCDDEFGGJKKMNNOPSSWW95 James Gateley ,
Miriam Blatt ,
Dennis Chen ,
Scott Cooke ,
Piyush Desai ,
Manjunath Doreswamy ,
Mark Elgood ,
Gary Feierbach ,
Tim Goldsbury ,
Dale Greenley ,
Raju Joshi ,
Mike Khosraviani ,
Robert Kwong ,
Manish Motwani ,
Chitresh Narasimhaiah ,
Sam J. Nicolino Jr. ,
Tooru Ozeki ,
Gary Peterson ,
Chris Salzmann ,
Nasser Shayesteh ,
Jeffrey Whitman ,
Pak Wong :
UltraSPARC-I Emulation.
13-18
Power Considerations in Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Technology and Layout Dependent Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Ted Stanion ,
Carl Sechen :
A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis.
60-64
export record as
dblp key:
export record as
dblp key:
Issues in EDA Frameworks
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel:
Managing Design Process Change - Lessons Learned
Scheduling and Retiming in Architectural Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/dac/DeCastelo-Vide-e-SouzaPP95
Delay Test and Diagnosis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/dac/VenkataramanHFRCP95
Discrete-Event Simulation
export record as
dblp key:
export record as
dblp key:
Peter A. Walker ,
Sumit Ghosh :
Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors.
144-150
export record as
dblp key:
Panel:
Power Minimization in IC Design
Storage Synthesis and Optimization
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Retiming and Sequential ATPG
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Partitioning and Placement
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Design Case Studies
export record as
dblp key:
Thomas W. Albrecht :
Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation.
222-227
export record as
dblp key:
export record as
dblp key:
Panel:
University-Industry Ties:
How Can They Be Improved?
Low Power Design
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Extraction and Module Generation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Advanced Methods in Practice
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Sequential Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Fault Modeling and Simulation
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
CAD for Interconnect
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Vasant B. Rao :
Delay Analysis of the Distributed RC Line.
370-375
export record as
dblp key:
export record as
dblp key:
Tutorial:
ASIC Prototyping
Datapath Synthesis and Modeling
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Learning and Counterexamples in Formal Verification
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Analog CAD
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel:
DOS, Windows, UNIX:
EDA and the O.S. War
Software Analysis and Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Electrical Simulation
export record as
dblp key:
export record as
dblp key:
conf/dac/TelicheveskyKW95 export record as
dblp key:
Optimization of Clock and Power Distribution
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Concurrent Engineering
export record as
dblp key:
conf/dac/SmailagicSAKMS95 export record as
dblp key:
export record as
dblp key:
Panel:
The ESDA Landscape:
Who Will Dominate?
Formal Verification of Arithmetic Circuits
export record as
dblp key:
export record as
dblp key:
Shinji Kimura :
Residue BDD and Its Application to the Verification of Arithmetic Circuits.
542-545
export record as
dblp key:
Routing for FPGAs
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
EDA and the WWW
export record as
dblp key:
Panel:
The Impact of the World Wide Web on Electronic Design and EDA
Code Generation for Embedded Systems
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Switching Activity and Power Analysis
export record as
dblp key:
Farid N. Najm :
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits.
612-617
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Combinational Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Panel:
Deep Submicron Design Challenges
Complexity Measures for VHDL
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Timing Analysis and Optimization
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Asynchronous Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/dac/VanbekbergenWK95
data released under the ODC-BY 1.0 license
