32. DAC 1995: San Francisco, California, USA

Design of UltraSPARC

Power Considerations in Synthesis

Technology and Layout Dependent Synthesis

Issues in EDA Frameworks

Panel: Managing Design Process Change - Lessons Learned

Scheduling and Retiming in Architectural Synthesis

Delay Test and Diagnosis

Discrete-Event Simulation

Panel: Power Minimization in IC Design

Storage Synthesis and Optimization

Retiming and Sequential ATPG

Partitioning and Placement

Design Case Studies

Panel: University-Industry Ties: How Can They Be Improved?

Low Power Design

Extraction and Module Generation

Advanced Methods in Practice

Sequential Logic Synthesis

Fault Modeling and Simulation

CAD for Interconnect

Tutorial: ASIC Prototyping

Datapath Synthesis and Modeling

Learning and Counterexamples in Formal Verification

Analog CAD

Panel: DOS, Windows, UNIX: EDA and the O.S. War

Software Analysis and Synthesis

Electrical Simulation

Optimization of Clock and Power Distribution

Concurrent Engineering

Panel: The ESDA Landscape: Who Will Dominate?

Formal Verification of Arithmetic Circuits

Routing for FPGAs

EDA and the WWW

Panel: The Impact of the World Wide Web on Electronic Design and EDA

Code Generation for Embedded Systems

Switching Activity and Power Analysis

Combinational Logic Synthesis

Panel: Deep Submicron Design Challenges

Complexity Measures for VHDL

Timing Analysis and Optimization

Asynchronous Synthesis

maintained by Schloss Dagstuhl LZI at University of Trier