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"Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay ..."

Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi (1995)

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DOI: 10.1145/217474.217612

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/dac/MenezesPP95
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  - https://dblp.org/rec/conf/dac/MenezesPP95
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi:
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC 1995: 690-695

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