ASP-DAC 2007: Yokohama, Japan

• Rob A. Rutenbar:
  Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains.
  
• Takayasu Sakurai:
  Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future".
  
• Fu-Chieh Hsu:
  How Foundry can Help Improve your Bottom-Line? Accuracy Matters!
  
• Subarna Sinha, Jianfeng Luo, Charles Chiang:
  Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process. 1-6
  
• David M. Pawlowski, Liang Deng, Martin D. F. Wong:
  Fast and Accurate OPC for Standard-Cell Layouts. 7-12
  
• Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang:
  Coupling-aware Dummy Metal Insertion for Lithography. 13-18
  
• Ruiming Chen, Hai Zhou:
  Fast Buffer Insertion for Yield Optimization Under Process Variations. 19-24
  
• Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman:
  A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. 24-31
  
• Axel Siebenborn, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
  Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. 32-37
  
• Márcio Oyamada, Flávio Rech Wagner, Marius Bonaciu, Wander O. Cesário, Ahmed Amine Jerraya:
  Software Performance Estimation in MPSoC Design. 38-43
  
• Woo-Chul Jeun, Soonhoi Ha:
  Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS. 44-49
  
• Pramod Chandraiah, Junyu Peng, Rainer Dömer:
  Creating Explicit Communication in SoC Models Using Interactive Re-Coding. 50-55
  
• Siddharth Choudhuri, Tony Givargis:
  System Architecture for Software Peripherals. 56-61
  
• Xiren Wang, Wenjian Yu, Zeyi Wang:
  A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates. 62-67
  
• Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud:
  Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers. 68-73
  
• Michael Chan, Adam Postula, Yong Ding:
  PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool. 74-79
  
• Mahta Jenabi, Noushin Riahi, Ali Fotowat-Ahmady:
  A Programmable Fully-Integrated GPS receiver in 0.18µm CMOS with Test Circuits. 80-85
  
• Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab:
  Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. 86-91
  
• Noriyuki Miura, Tadahiro Kuroda:
  A 1Tb/s 3W Inductive-Coupling Transceiver Chip. 92-93
  
• Ahmet Oncu, B. B. M. Wasanthamala Badalawa, Tong Wang, Minoru Fujishima:
  22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors. 94-95
  
• Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Masao Hotta:
  A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. 96-97
  
• K. Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu:
  A Wideband CMOS LC-VCO Using Variable Inductor. 98-99
  
• Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
  Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. 100-101
  
• Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu:
  A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. 102-103
  
• Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu:
  Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. 104-105
  
• Ivan C. H. Ivan Chee Hong Lai, M. Fujishima:
  Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems. 106-107
  
• Roel Pantonial, Md. Ashfaquzzaman Khan, Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi:
  Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique. 108-109
  
• Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu:
  Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. 110-111
  
• Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, Wei-Cheng Hung, Kai-Yuan Jan:
  A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform. 112-113
  
• Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang:
  Configurable AMBA On-Chip Real-Time Signal Tracer. 114-115
  
• Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, T. Nakamura, H. Takasu:
  Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. 116-117
  
• Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu:
  A Multi-Drop Transmission-Line Interconnect in Si LSI. 118-119
  
• Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera:
  A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. 120-121
  
• Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera:
  A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. 122-123
  
• M. Watanabe, F. Kobayashi:
  A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. 124-125
  
• Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi:
  Low-Power High-Speed 180-nm CMOS Clock Drivers. 126-127
  
• Ameya R. Agnihotri, Patrick H. Madden:
  Fast Analytic Placement using Minimum Cost Flow. 128-134
  
• Natarajan Viswanathan, Min Pan, Chris C. N. Chu:
  FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. 135-140
  
• Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
  Hippocrates: First-Do-No-Harm Detailed Placement. 141-146
  
• Jarrod A. Roy, Igor L. Markov:
  ECO-system: Embracing the Change in Placement. 147-152
  
• Satoshi Ono, Sameer Tilak, Patrick H. Madden:
  Bisection Based Placement for the X Architecture. 153-158
  
• Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, Naehyuck Chang, Eui-Young Chung:
  Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems. 159-164
  
• Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou:
  A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. 165-170
  
• Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi:
  Communication Architecture Synthesis of Cascaded Bus Matrix. 171-177
  
• Jin Guo, Antonis Papanikolaou, Francky Catthoor:
  Topology exploration for energy efficient intra-tile communication. 178-183
  
• Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
  Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. 184-190
  
• Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong:
  Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. 191-196
  
• Guoyong Shi, Weiwei Chen, C.-J. Richard Shi:
  A Graph Reduction Approach to Symbolic Circuit Analysis. 197-202
  
• Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, Xuan Zeng:
  Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic. 203-208
  
• Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng:
  WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. 209-214
  
• Shigetoshi Nakatake:
  Structured Placement with Topological Regularity Evaluation. 215-220
  
• Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvin Y. Y. Doong, Keh-Jeng Chang:
  Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM. 221-225
  
• N. Verghese, P. Hurat:
  DFM reality in sub-nanometer IC design. 226-231
  
• Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai:
  DFM/DFY practices during physical designs for timing, signal integrity, and power. 232-237
  
• Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang:
  Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. 238-243
  
• Min Pan, Chris C. N. Chu, Priyadarshan Patra:
  A Novel Performance-Driven Topology Design Algorithm. 244-249
  
• Min Pan, Chris C. N. Chu:
  FastRoute 2.0: A High-quality and Efficient Global Router. 250-255
  
• Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong:
  DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. 256-261
  
• Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang:
  A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. 262-267
  
• Tan Yan, Shuting Li, Yasuhiro Takashima, H. Murata:
  A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. 268-273
  
• Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
  LEAF: A System Level Leakage-Aware Floorplanner for SoCs. 274-279
  
• Shigeru Watanabe, Kenshu Seto, Y. Ishikawa, Satoshi Komatsu, Masahiro Fujita:
  Protocol Transducer Synthesis using Divide and Conquer approach. 280-285
  
• Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
  A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. 286-291
  
• Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. 292-297
  
• Soumyajit Dey, Monu Kedia, Anupam Basu:
  Architectural Optimizations for Text to Speech Synthesis in Embedded Systems. 298-303
  
• Roy Armoni, Limor Fix, Ranan Fraer, Tamir Heyman, Moshe Y. Vardi, Yakir Vizel, Yael Zbar:
  Deeper Bound in BMC by Combining Constant Propagation and Abstraction. 304-309
  
• Malay K. Ganai, Aarti Gupta:
  Efficient BMC for Multi-Clock Systems with Clocked Specifications. 310-315
  
• David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda:
  Symbolic Model Checking of Analog/Mixed-Signal Circuits. 316-323
  
• Marc Boule, Zeljko Zilic:
  Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. 324-329
  
• Soonhoi Ha:
  Model-based Programming Environment of Embedded Software for MPSoC. 330-335
  
• Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
  RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. 336-341
  
• Jian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo, Chi-Sheng Shih:
  Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems. 342-349
  
• Hiroaki Inoue, Masato Edahiro, Junji Sakai:
  Towards scalable and secure execution platform for embedded systems. 350-354
  
• Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy:
  Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. 355-360
  
• S. Dabas, Ning Dong, Jaijeet S. Roychowdhury:
  Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. 361-366
  
• Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang:
  Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. 367-372
  
• Arthur Nieuwoudt, Mehboob Alam, Yehia Massoud:
  Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation. 373-378
  
• Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud:
  Frequency Selective Model Order Reduction via Spectral Zero Projection. 379-383
  
• Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
  Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. 384-389
  
• Patrice Gerin, Hao Shen, A. Chureau, Aimen Bouchhima, Ahmed Amine Jerraya:
  Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC. 390-395
  
• Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng:
  A Retargetable Software Timing Analyzer Using Architecture Description Language. 396-401
  
• Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton:
  Automating Logic Rectification by Approximate SPFDs. 402-407
  
• Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
  BddCut: Towards Scalable Symbolic Cut Enumeration. 408-413
  
• Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
  Node Mergers in the Presence of Don't Cares. 414-419
  
• Min-Lun Chuang, Chun-Yao Wang:
  Synthesis of Reversible Sequential Elements. 420-425
  
• Tsung-Lin Lee, Chun-Yao Wang:
  Recognition of Fanout-free Functions. 426-431
  
• Georges G. E. Gielen:
  Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies. 432-437
  
• S. Yoshitomi:
  Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits. 438-441
  
• Xiaolue Lai, Jaijeet S. Roychowdhury:
  Advanced tools for simulation and design of oscillators/PLLs. 442-449
  
• Ying Zhou, Zhuo Li, Yuxin Tian, Weiping Shi, Frank Liu:
  A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. 450-455
  
• Youngmin Kim, Dusan Petranovic, Dennis Sylvester:
  Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. 456-461
  
• Ruiming Chen, Hai Zhou:
  New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. 462-467
  
• Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang:
  Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method. 468-473
  
• Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles Chiang:
  Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. 474-479
  
• Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee:
  Retiming for Synchronous Data Flow Graphs. 480-485
  
• Ilie I. Luican, Hongwei Zhu, Florin Balasa:
  Signal-to-Memory Mapping Analysis for Multimedia Signal Processing. 486-491
  
• T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
  MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. 492-497
  
• Udaya Seshua, Nagaraju Bussa, Bart Vermeulen:
  A Run-Time Memory Protection Methodology. 498-503
  
• Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau:
  Short-Circuit Compiler Transformation: Optimizing Conditional Blocks. 504-510
  
• Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu:
  Optimization of Arithmetic Datapaths with Finite Word-Length Operands. 511-516
  
• M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig:
  Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection. 517-522
  
• Yazhuo Dong, Yong Dou:
  A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications. 523-528
  
• Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang:
  High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. 529-534
  
• Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
  Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. 535-540
  
• Chuan Lin, Hai Zhou:
  Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. 541-546
  
• Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim:
  An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. 547-552
  
• Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud:
  Fast Electrical Correction Using Resizing and Buffering. 553-558
  
• Sanghamitra Roy, Charlie Chung-Ping Chen:
  SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. 559-564
  
• Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue:
  Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. 565-570
  
• Hwisung Jung, Andy Hwang, Massoud Pedram:
  Flow-Through-Queue based Power Management for Gigabit Ethernet Controller. 571-576
  
• Christopher Ostler, Karam S. Chatha, Goran Konjevod:
  Approximation Algorithm for Process Mapping on Network Processor Architectures. 577-582
  
• Zahid Khan, Tughrul Arslan:
  Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture. 583-588
  
• Imran Ahmed, Tughrul Arslan:
  VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond. 589-594
  
• Shin-Yi Lin, Chih-Tsun Huang:
  A High-Throughput Low-Power AES Cipher for Network Applications. 595-600
  
• Ajay K. Verma, Paolo Ienne:
  Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. 601-608
  
• Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis:
  Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. 609-615
  
• Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris:
  An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. 616-621
  
• Cheoljoo Jeong, Steven M. Nowick:
  Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation. 622-627
  
• Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
  Safe Delay Optimization for Physical Synthesis. 628-633
  
• Kimiyoshi Usami:
  Overview on Low Power SoC Design Technology. 634-636
  
• M. Hase, K. Akie, M. Nobori, K. Matsumoto:
  Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware. 637-643
  
• K. Mori, M. Suzuki, Y. Ohara, S. Matsuo, A. Asano:
  Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G). 644-648
  
• Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita:
  Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier". 649-653
  
• Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi:
  Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. 654-659
  
• Yu-Shiang Lin, Dennis Sylvester:
  Runtime leakage power estimation technique for combinational circuits. 660-665
  
• Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
  Logic and Layout Aware Voltage Island Generation for Low Power Design. 666-671
  
• Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen:
  A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. 672-677
  
• Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
  A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs. 678-683
  
• Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen:
  Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. 684-689
  
• Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang:
  Delay Uncertainty Reduction by Interconnect and Gate Splitting. 690-695
  
• Charbel J. Akl, Magdy A. Bayoumi:
  Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects. 696-701
  
• Tien-Ting Fang, Ting-Chi Wang:
  Fast Buffered Delay Estimation Considering Process Variations. 702-707
  
• Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud:
  Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect. 708-713
  
• Dan Zhao, Unni Chandran, Hideo Fujiwara:
  Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. 714-719
  
• Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
  Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. 720-725
  
• Erik Larsson, Jon Persson:
  An Architecture for Combined Test Data Compression and Abort-on-Fail Test. 726-731
  
• Hao Fang, Chenguang Tong, Xu Cheng:
  RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power. 732-737
  
• Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda:
  Systematic Scan Reconfiguration. 738-743
  
• David Goodwin, Chris Rowen, Grant Martin:
  Configurable Multi-Processor Platforms for Next Generation Embedded Systems. 744-746
  
• Kazuyuki Hirata, John Goodacre:
  ARM MPCore; The streamlined and scalable ARM11 processor core. 747-748
  
• Maurizio Paganini:
  Nomadik®: A Mobile Multimedia Application Processor Platform. 749-750
  
• Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan:
  Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. 751-756
  
• Sanjay Pant, David Blaauw:
  Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks. 757-762
  
• Yu Zhong, Martin D. F. Wong:
  Fast Placement Optimization of Power Supply Pads. 763-767
  
• Yu Zhong, Martin D. F. Wong:
  Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid. 768-773
  
• Hanif Fatemi, Shahin Nazarian, Massoud Pedram:
  A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms. 774-779
  
• Jason Cong, Guojie Luo, Jie Wei, Yan Zhang:
  Thermal-Aware 3D IC Placement Via Transformation. 780-785
  
• Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee:
  Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. 786-791
  
• Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
  On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. 792-797
  
• Wai-Kei Mak, Jr-Wei Chen:
  Voltage Island Generation under Performance Requirement for SoC Designs. 798-803
  
• Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen:
  Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. 804-809
  
• Seongmoon Wang, Wenlong Wei:
  A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture. 810-816
  
• Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz:
  Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. 817-822
  
• Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar:
  AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. 823-828
  
• Yu-Ru Hong, Juinn-Dar Huang:
  Fault Dictionary Size Reduction for Million-Gate Large Circuits. 829-834
  
• Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li:
  Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies. 835-840
  
• Atsushi Hiraishi, Toshio Sugano, Hideki Kusamitsu:
  Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation. 841-845
  
• David W. Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane, Jeff Johnson:
  Xbox360^TM Front Side Bus - A 21.6 GB/s End-to-End Interface Design. 846-853
  
• Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone:
  Design Consideration of 6.25 Gbps Signaling for High-Performance Server. 854-857
  
• Wai-Yeung Yip, Scott Best, Wendemagegnehu T. Beyene, Ralf Schmitt:
  System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production. 858-865
  
• Jian-Jia Chen, Kazuo Iwama, Tei-Wei Kuo, Hsueh-I Lu:
  Flow Time Minimization under Energy Constraints. 866-871
  
• Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou:
  Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost. 872-877
  
• Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura:
  A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. 878-883
  
• Subhasis Banerjee, G. Surendra, S. K. Nandy:
  Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. 884-889
  
• Jorgen Peddersen, Sri Parameswaran:
  CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. 890-895
  
• Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda:
  Design Methodology for 2.4GHz Dual-Core Microprocessor. 896-901
  
• Fu-Ching Yang, Ing-Jer Huang:
  An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools. 902-907
  
• Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan:
  A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications. 908-913
  
• Giacomo Paci, Paul Marchal, Luca Benini:
  Exploration of Low Power Adders for a SIMD Data Path. 914-919
  
• Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
  Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. 920-925
  
• Matthew D. T. Lewis, Tobias Schubert, Bernd Becker:
  Multithreaded SAT Solving. 926-931
  
• Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian:
  Trace Compaction using SAT-based Reachability Analysis. 932-937
  
• Stefan Disch, Christoph Scholl:
  Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets. 938-943
  
• Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
  Fixing Design Errors with Counterexamples and Resynthesis. 944-949
  

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