Fumiyasu Hirose (Ed.):
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006.
IEEE 2006, ISBN 0-7803-9451-8 Keynote address I
export record as
dblp key:
conf/aspdac/Sangiovanni-Vincentelli06
Keynote address II
export record as
dblp key:
Keynote address III
export record as
dblp key:
Yukichi Niwa :
Effective platform-based development for large-scale systems design.
Formal methods for coverage and scalable verification
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Interconnect for high-end SoC
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Muhammad Omer Cheema ,
Omar Hammami :
Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization.
54-60
Timing analysis and optimization
export record as
dblp key:
conf/aspdac/RamalingamKDP06 export record as
dblp key:
conf/aspdac/NazarianPLT06 export record as
dblp key:
export record as
dblp key:
conf/aspdac/ShrivastavaPPV06 export record as
dblp key:
University design contest
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/aspdac/FukazawaNNT06 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/aspdac/IshikawaSIG06 export record as
dblp key:
conf/aspdac/RahmatullahN06 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/aspdac/NishimuraMSMKKEY06 export record as
dblp key:
Software techniques for efficient SoC design
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Application examples with leading edge design methodology
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/aspdac/YamaokaMAKM06 export record as
dblp key:
Placement
export record as
dblp key:
export record as
dblp key:
conf/aspdac/ViswanathanPC06 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Special session:
electrothermal design of nanoscale integrated circuits
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Ja Chun Ku ,
Yehea I. Ismail :
Area optimization for leakage reduction and thermal stability in nanometer scale technologies.
231-236
export record as
dblp key:
conf/aspdac/BansalMSCMR06
Logic Synthesis
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/aspdac/YamashitaTTOT06
Future technical directions for design automation
export record as
dblp key:
Xiaolue Lai ,
Jaijeet S. Roychowdhury :
Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena.
273-278
export record as
dblp key:
conf/aspdac/McCorquodaleMB06 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Routing and interconnect optimization
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Zhuo Li ,
Weiping Shi :
An O (mn ) time algorithm for optimal buffer insertion of nets with m sinks.
320-325
export record as
dblp key:
Man Chung Hon :
Spec-based flip-flop and latch repeater planning.
326-331
Special session:
flash memory in embedded systems
export record as
dblp key:
export record as
dblp key:
Resolving timing issues:
design and test
export record as
dblp key:
conf/aspdac/ItoKMYMSEYKIAHNSN06 Noriyuki Ito ,
Akira Kanuma ,
Daisuke Maruyama ,
Hitoshi Yamanaka ,
Tsuyoshi Mochizuki ,
Osamu Sugawara ,
Chihiro Endoh ,
Masahiro Yanagida ,
Takeshi Kono ,
Yutaka Isoda ,
Kazunobu Adachi ,
Takahisa Hiraide ,
Shigeru Nagasawa ,
Yaroku Sugiyama ,
Eizo Ninoi :
Delay defect screening for a 2.16GHz SPARC64 microprocessor.
342-347
export record as
dblp key:
conf/aspdac/FukunagaKWMHS06 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Leading edge design methodology for SoCs and SiPs
export record as
dblp key:
conf/aspdac/BonaciuBYCCJ06 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Advanced circuit simulation
export record as
dblp key:
Zhao Li ,
C.-J. Richard Shi :
A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings.
402-407
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Special session:
open access overview
export record as
dblp key:
export record as
dblp key:
Yoshio Inoue :
Open access overview "industrial experience".
437-438
export record as
dblp key:
export record as
dblp key:
Advances in simulation technologies
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Junghee Lee ,
Joonhwan Yi :
Cycle error correction in asynchronous clock modeling for cycle-based simulation.
460-465
export record as
dblp key:
Scheduling for embedded systems
export record as
dblp key:
Peng Rong ,
Massoud Pedram :
Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system.
473-478
export record as
dblp key:
export record as
dblp key:
conf/aspdac/PosadasASVB06 export record as
dblp key:
export record as
dblp key:
High frequency interconnect effects in nanometer technology
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Designers' forum:
low power design
export record as
dblp key:
conf/aspdac/KitaharaHSTYUM06 export record as
dblp key:
export record as
dblp key:
conf/aspdac/OnouchiYMMS06 export record as
dblp key:
Power optimization of large-scale circuits
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Advanced memory and processor architectures for MPSoC
export record as
dblp key:
export record as
dblp key:
conf/aspdac/KoharaTUMTYO06 export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
conf/aspdac/JanapsatyaIP06
New routing techniques
export record as
dblp key:
export record as
dblp key:
conf/aspdac/ItoKYISKTYNIAMIS06 Noriyuki Ito ,
Hideaki Katagiri ,
Ryoichi Yamashita ,
Hiroshi Ikeda ,
Hiroyuki Sugiyama ,
Hiroaki Komatsu ,
Yoshiyasu Tanamura ,
Akihiro Yoshitake ,
Kazuhiro Nonomura ,
Kinya Ishizaka ,
Hiroaki Adachi ,
Yutaka Mori ,
Yutaka Isoda ,
Yaroku Sugiyama :
Diagonal routing in high performance microprocessor design.
624-629
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Minimization of test cost and power
export record as
dblp key:
X.-L. Huang ,
J.-L. Huang :
A routability constrained scan chain ordering technique for test power reduction.
648-652
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Substrate coupling and analog synthesis
export record as
dblp key:
Daisuke Kosaka ,
Makoto Nagata :
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation.
677-682
export record as
dblp key:
Xiren Wang ,
Wenjian Yu ,
Zeyi Wang :
A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles.
683-688
export record as
dblp key:
Zuochang Ye ,
Zhiping Yu :
Parasitics extraction involving 3-D conductors based on multi-layered Green's function.
689-693
export record as
dblp key:
export record as
dblp key:
Xiaoying Wang ,
Lars Hedrich :
An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis.
700-705
Statistical and yield analysis
export record as
dblp key:
Kenta Yamada ,
Noriaki Oda :
Statistical corner conditions of interconnect delay (corner LPE specifications).
706-711
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Special session:
H.264/AVC design challenges and solutions
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Floorplanning
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Chien-Chang Chen ,
Wai-Kei Mak :
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers.
777-782
export record as
dblp key:
export record as
dblp key:
Memory optimization for embedded systems
export record as
dblp key:
conf/aspdac/JanapsatyaIP06a export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
export record as
dblp key:
Inductive issues in power grids and packages
export record as
dblp key:
export record as
dblp key:
conf/aspdac/WatanabeTKA06 export record as
dblp key:
export record as
dblp key:
Changhao Yan ,
Wenjian Yu ,
Zeyi Wang :
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.
844-849
export record as
dblp key:
Designers' forum:
"cell" processor
export record as
dblp key:
export record as
dblp key:
conf/aspdac/WatanabeSMBMSH06 export record as
dblp key:
conf/aspdac/ChaudhrySPD06 export record as
dblp key:
conf/aspdac/PhamABBGHHJKKKLLNPPPPRVWWW06 Dac Pham ,
Hans-Werner Anderson ,
Erwin Behnen ,
Mark Bolliger ,
Sanjay Gupta ,
H. Peter Hofstee ,
Paul E. Harvey ,
Charles R. Johns ,
James A. Kahle ,
Atsushi Kameyama ,
John M. Keaty ,
Bob Le ,
Sang Lee ,
Tuyen V. Nguyen ,
John G. Petrovick ,
Mydung Pham ,
Juergen Pille ,
Stephen D. Posluszny ,
Mack W. Riley ,
Joseph Verock ,
James D. Warnock ,
Steve Weitzel ,
Dieter F. Wendel :
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.
871-878
High-level synthesis
export record as
dblp key:
export record as
dblp key:
Yu Pu ,
Yajun Ha :
An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model.
886-891
export record as
dblp key:
export record as
dblp key:
conf/aspdac/CordoneFSPS06 export record as
dblp key:
Modeling, compilation and optimization of embedded architectures
export record as
dblp key:
export record as
dblp key:
Yen-Jen Chang :
Lazy BTB: reduce BTB energy consumption using dynamic profiling.
917-922
export record as
dblp key:
export record as
dblp key:
conf/aspdac/UnnikrishnanKL06 export record as
dblp key:
Statistical design
export record as
dblp key:
export record as
dblp key:
conf/aspdac/AbbaspourFP06 export record as
dblp key:
export record as
dblp key:
conf/aspdac/EkpanyapongWL06 export record as
dblp key:
data released under the ODC-BY 1.0 license
