ITC 2001:
Baltimore, MD, USASession 2: IEE 1149 - Beyond DC Testing At Board Test
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Session 3: Bist Medley
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Session 4: How Can We Improve Iddq Testing for DSM/VDSM?
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Session 5: Practical Experience With SOC Testing
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Session 6: Some Thorny Problems For Ate Software
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A. T. Sivaram :
Split timing mode (STM)-answer to dual frequency domain testing.
140-147
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Session 7: Lecture Series: Test and Repair Of Large Embedded Drams
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conf/itc/NaguraMSFFOKOTDAKT01 Yoshihiro Nagura ,
Michael Mullins ,
Anthony Sauvageau ,
Yoshinoro Fujiwara ,
Katsuya Furue ,
Ryuji Ohmura ,
Tatsunori Komoike ,
Takenori Okitaka ,
Tetsushi Tanizaki ,
Katsumi Dosaka ,
Kazutami Arimoto ,
Yukiyoshi Koda ,
Tetsuo Tada :
Test cost reduction by at-speed BISR for embedded DRAMs.
182-187
Session 8: DFT Innovations
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Session 9: On-line Test
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Kaijie Wu ,
Ramesh Karri :
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique.
221-229
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Karl Thaller :
A highly-efficient transparent online memory test.
230-239
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Session 10: Novel Techniques For Fault Diagnosis
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conf/itc/BartensteinHHS01
Session 11: Testing Above GigaHertz
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Bernd Laquai ,
Yi Cai :
Testing gigabit multilane SerDes interfaces with passive jitter injection filters.
297-304
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conf/itc/YamaguchiSNHRI01
Session 12: Test Methods For High-density Modules
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Session 13: High-quality Test
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Session 14: New IDDX and Energy Test Techniques
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Session 15: ATE Hardware: Improving Your Test Results
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Session 16: Advanced Microprocessor Test Methodologies
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Session 17: Lecture Series - Solving Board Test and In-System Problems
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Alan Albee :
A practical guide to combining ICT & boundary scan testing.
487-494
Session 18: Mixed-Signal Test Techniques
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Solomon Max :
Ramp testing of ADC transition levels using finite resolution ramps.
495-501
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Udaya Natarajan :
Test challenges for SONET/SDH physical layer OC3 devices and beyond.
502-511
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Session 19: Advanced Techniques for Embedded Core Testing
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Session 20: Test Generation for Crosstalk Faults
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Session 21: Microprocessor Testing
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Gilbert Vandling :
Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo.
593-599
Session 22: Standards and Techniques - Board Test Development
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Session 23: Delay Test
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Jeff Rearick :
Too much delay fault coverage is a bad thing.
624-633
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Session 24: Ideas for Low-Power Scan Operation
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Session 25: Uncovering and Understanding Why Circuits Fail
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conf/itc/KrishnaswamyMV01 export record as
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Session 26: ATE HW: Conquering Those Stubborn Test Problems
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Jamie Cullen :
Scan test sequencing hardware for structural test.
713-720
Session 27: Advances in Scan Testing
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conf/itc/BarnhartBDFKKF01
Session 28: Memory Testing
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Session 29: Increasing Design Validation Coverage
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Session 30: PLL AND Jitter Testing
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Seongwon Kim ,
Mani Soma :
Test evaluation and data on defect-oriented BIST architecture for high-speed PLL.
830-837
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Masashi Shimanouchi :
An approach to consistent jitter modeling for various jitter aspects and measurement methods.
848-857
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Session 31: New Ideas for BIST TPG
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Seongrnoon Wang :
Low hardware overhead scan based 3-weight weighted random BIST.
868-877
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Session 32: Test Automation; Improbing IC Test Efficiency
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Session 33: FPGA Testing
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Session 34: RF Testing
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Session 35: Embedded Memories Test and Repair
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conf/itc/JakobsenDPABNLB01 export record as
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Session 36: Lecture Series - Logic BIST Case Studies
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Session 37: Advanced Methods in Embedded Core Test
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Session 38: How Could We Model and Test VDSM Defects
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Session 39: Practical Test Generation Techniques
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Session 40: Delving into Factors Affecting Manufacturing Cost
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conf/itc/ThiagarajanTrichySRS01 export record as
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Session 41: ATE Hardware: From GigaHertz to TeraHertz
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John Cheng :
When zero picoseconds edge placement accuracy is not enough.
1134-1142
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ITC 2000 Best Paper
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