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FeiFei Zhao
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2010 – 2019
- 2010
- [c2]Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang:
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT 2010: 358-366
2000 – 2009
- 2009
- [c1]Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang:
Logic BIST Architecture for System-Level Test and Diagnosis. Asian Test Symposium 2009: 21-26
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last updated on 2024-04-24 22:51 CEST by the dblp team
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