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ORCIDHafizur Rahaman 0001
Person information
- affiliation: Indian Institute of Engineering Science and Technology, Shibpur, India
- affiliation (former): University of Bristol, UK
- affiliation (former): Jadavpur University, Kolkata, India
Other persons with the same name
- Hafizur Rahaman 0002
![[0000-0003-0858-3821]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-0858-3821")
— Curtin University, Perth, Australia (and 2 more)
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Journal Articles
- 2022
[j81]Sudip Ghosh, Yuvam Bhateja, Joshua Roy Palathinkal, Hafizur Rahaman:
Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR. Circuits Syst. Signal Process. 41(2): 867-891 (2022)- [j80]Manas Parai, Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman:
Multi-source data fusion technique for parametric fault diagnosis in analog circuits. Integr. 84: 92-101 (2022) - [j79]Joyati Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das, Bhargab B. Bhattacharya:
DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits. J. Circuits Syst. Comput. 31(10): 2250128:1-2250128:24 (2022) - [j78]Rakesh Das, Chandan Bandyopadhyay, Hafizur Rahaman:
An improved synthesis technique for optical circuits using MIG and XMG. Microelectron. J. 120: 105341 (2022) - [j77]Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation. Microelectron. J. 128: 105535 (2022) - [j76]Pampa Howladar, Pranab Roy, Hafizur Rahaman:
MEDA Based Biochips: Detection, Prevention and Rectification Techniques for Cyberphysical Attacks. IEEE ACM Trans. Comput. Biol. Bioinform. 19(4): 2345-2355 (2022) - 2021
- [j75]Abhishek Kar, Mitiko Miura-Mattausch, Mainak Sengupta, Dondee Navarro, Hideyuki Kikuchihara, Takahiro Iizuka, Hafizur Rahaman, Hans Jürgen Mattausch:
Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation. IEEE Access 9: 23786-23794 (2021) - [j74]Supriyo Srimani, Manas Parai, Kasturi Ghosh, Hafizur Rahaman:
A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov-Smirnov Test Method. Circuits Syst. Signal Process. 40(5): 2091-2113 (2021) - [j73]Laxmidhar Biswal, Bappaditya Mondal, Hafizur Rahaman:
Fault-tolerant quantum implementation of conventional decoder logic with enable input. IET Circuits Devices Syst. 15(5): 415-423 (2021) - [j72]Anindita Chakraborty, Vivek Maurya, Sneha Prasad, Suryansh Gupta, Rajat Subhra Chakraborty, Hafizur Rahaman:
Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices. IET Comput. Digit. Tech. 15(2): 112-124 (2021) - [j71]Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman:
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. Integr. 76: 40-54 (2021) - [j70]Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
An ant colony based mapping of quantum circuits to nearest neighbor architectures. Integr. 78: 11-24 (2021) - [j69]Anindita Chakraborty, Partha Sarathi Gupta, Ritika Singh, Rakesh Das, Hafizur Rahaman:
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC). Integr. 81: 254-267 (2021) - [j68]Subhashree Basu, Malay Kule, Hafizur Rahaman:
Implementation of Symmetric Functions Using Memristive Nanocrossbar Arrays and their Application in Cryptography. J. Circuits Syst. Comput. 30(12): 2150223:1-2150223:13 (2021) - [j67]Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman:
High Performance Kernel Architecture for Convolutional Neural Network Acceleration. J. Circuits Syst. Comput. 30(15): 2150266:1-2150266:21 (2021) - [j66]Pampa Howladar, Pranab Roy, Hafizur Rahaman:
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1451-1464 (2021) - 2020
- [j65]Manas Kumar Parai, Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman:
Analog Circuit Fault Detection by Impulse Response-Based Signature Analysis. Circuits Syst. Signal Process. 39(9): 4281-4296 (2020) - [j64]Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman:
Survey on memory management techniques in heterogeneous computing systems. IET Comput. Digit. Tech. 14(2): 47-60 (2020) - [j63]Anirban Bhattacharjee, Chandan Bandyopadhyay, Bappaditya Mondal, Hafizur Rahaman:
Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy. J. Circuits Syst. Comput. 29(16): 2050263:1-2050263:26 (2020) - 2019
- [j62]Arnab Mukhopadhyay, Tapas Kumar Maiti, Sandip Bhattacharya, Takahiro Iizuka, Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Hafizur Rahaman, Sadayuki Yoshitomi, Dondee Navarro, Hans Jürgen Mattausch:
Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs. IEICE Trans. Electron. 102-C(6): 487-494 (2019) - [j61]Sudipta Bardhan, Manodipan Sahoo, Hafizur Rahaman:
Boltzmann transport equation-based semi-classical drain current model for bilayer GFET including scattering effects. IET Circuits Devices Syst. 13(4): 456-464 (2019) - [j60]Chandan Bandyopadhyay, Rakesh Das, Anupam Chattopadhyay, Hafizur Rahaman:
Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures. IET Comput. Digit. Tech. 13(1): 38-48 (2019) - [j59]Tanusree Kaibartta, Chandan Giri, Hafizur Rahaman, Debesh Kumar Das:
Approach of genetic algorithm for power-aware testing of 3D IC. IET Comput. Digit. Tech. 13(5): 383-396 (2019) - [j58]Rupam Bhattacharya, Pranab Roy, Hafizur Rahaman:
A Complete Routing Simulator for Digital Microfluidic Biochip. Int. J. Inf. Syst. Model. Des. 10(2): 70-85 (2019) - [j57]Anindita Chakraborty, Vivek Saurabh, Partha Sarathi Gupta, Rituraj Kumar, Saikat Majumdar, Smriti Das, Hafizur Rahaman:
In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC). Integr. 66: 24-34 (2019) - [j56]Sabir Ali Mondal, Pradip Mandal, Hafizur Rahaman:
Fast locking, startup-circuit free, low area, 32-phase analog DLL. Integr. 66: 60-66 (2019) - [j55]Malay Kule, Hafizur Rahaman, Bhargab B. Bhattacharya:
Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults. J. Circuits Syst. Comput. 28(11): 1950180:1-1950180:22 (2019) - [j54]Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das:
Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits. J. Circuits Syst. Comput. 28(12): 1950212:1-1950212:18 (2019) - [j53]Sudipta Bardhan, Manodipan Sahoo, Hafizur Rahaman:
A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field Effect Transistor Including the Capacitive Effects. J. Circuits Syst. Comput. 28(14): 1950241:1-1950241:19 (2019) - [j52]Pampa Howladar, Pranab Roy, Hafizur Rahaman:
A High-performance Homogeneous Droplet Routing Technique for MEDA-based Biochips. ACM J. Emerg. Technol. Comput. Syst. 15(4): 38:1-38:37 (2019) - [j51]Sudip Poddar, Robert Wille, Hafizur Rahaman, Bhargab B. Bhattacharya:
Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1886-1899 (2019) - 2018
- [j50]Subhajit Das, Sudip Ghosh, Nachiketa Das, Santi P. Maity, Hafizur Rahaman, Reshmi Maity, Niladri Maity:
Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach. Circuits Syst. Signal Process. 37(12): 5690 (2018) - [j49]Chandan Bandyopadhyay, Shalini Parekh, Hafizur Rahaman:
Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits. IET Comput. Digit. Tech. 12(4): 167-175 (2018) - [j48]Rupam Bhattacharya, Pranab Roy, Hafizur Rahaman:
Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation. Integr. 60: 74-91 (2018) - [j47]Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman:
Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network. J. Circuits Syst. Comput. 27(1): 1850001:1-1850001:17 (2018) - [j46]Sambaran Hazra, Sudip Ghosh, Sayandip De, Hafizur Rahaman:
FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time. J. Real Time Image Process. 14(1): 193-221 (2018) - [j45]Chandan Bandyopadhyay, Rakesh Das, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams. Microelectron. J. 71: 19-29 (2018) - [j44]Laxmidhar Biswal, Rakesh Das, Chandan Bandyopadhyay, Anupam Chattopadhyay, Hafizur Rahaman:
A template-based technique for efficient Clifford+T-based quantum circuit implementation. Microelectron. J. 81: 58-68 (2018) - 2017
- [j43]Manodipan Sahoo, Hafizur Rahaman:
Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects. J. Circuits Syst. Comput. 26(6): 1750102:1-1750102:21 (2017) - [j42]Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan:
Selected Articles from the IEEE ISED 2016 Conference. J. Low Power Electron. 13(4): 605-606 (2017) - 2016
- [j41]Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimization of Test Wrapper for TSV Based 3D SOCs. J. Electron. Test. 32(5): 511-529 (2016) - [j40]Debaprasad Das, Hafizur Rahaman:
Investigating the Applicability of Graphene Nanoribbon as Signal and Power Interconnects for Nanometer Designs. J. Circuits Syst. Comput. 25(2): 1650001:1-1650001:14 (2016) - [j39]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya:
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM J. Emerg. Technol. Comput. Syst. 12(4): 34:1-34:29 (2016) - [j38]Manodipan Sahoo, Hafizur Rahaman:
Modeling and analysis of crosstalk induced overshoot/undershoot effects in multilayer graphene nanoribbon interconnects and its impact on gate oxide reliability. Microelectron. Reliab. 63: 231-238 (2016) - [j37]Soumyajit Poddar, Prasun Ghosal, Hafizur Rahaman:
Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip. ACM Trans. Embed. Comput. Syst. 15(1): 2:1-2:30 (2016) - [j36]Pranab Roy, Swati Saha, Hafizur Rahaman, Parthasarathi Dasgupta:
Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3345-3358 (2016) - 2015
- [j35]Prasenjit Chanak, Indrajit Banerjee, Hafizur Rahaman:
Load management scheme for energy holes reduction in wireless sensor networks. Comput. Electr. Eng. 48: 343-357 (2015) - [j34]Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. IET Comput. Digit. Tech. 9(5): 268-274 (2015) - [j33]Manodipan Sahoo, Hafizur Rahaman:
Modeling of Crosstalk Induced Effects in Copper-Based Nanointerconnects: An ABCD Parameter Matrix-Based Approach. J. Circuits Syst. Comput. 24(2): 1540007:1-1540007:22 (2015) - [j32]Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan:
Selected Articles from the IEEE ISED 2014 Conference. J. Low Power Electron. 11(3): 373-374 (2015) - [j31]Sudip Ghosh, Arijit Biswas, Santi Prasad Maity, Hafizur Rahaman:
Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications. J. Low Power Electron. 11(3): 375-386 (2015) - [j30]Kamalika Datta, Indranil Sengupta, Hafizur Rahaman:
A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines. IEEE Trans. Computers 64(4): 1208-1214 (2015) - [j29]Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips. ACM Trans. Design Autom. Electr. Syst. 21(1): 17:1-17:33 (2015) - 2014
- [j28]Indrajit Banerjee, Prasenjit Chanak, Hafizur Rahaman, Tuhina Samanta:
Effective fault detection and routing scheme for wireless sensor networks. Comput. Electr. Eng. 40(2): 291-306 (2014) - [j27]Kamalika Datta, Gaurav Rathi, Indranil Sengupta, Hafizur Rahaman:
An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes. ACM J. Emerg. Technol. Comput. Syst. 11(2): 15:1-15:16 (2014) - [j26]Manodipan Sahoo, Hafizur Rahaman, Bhargab B. Bhattacharya:
On the Suitability of Single-Walled Carbon Nanotube Bundle Interconnects for High-Speed and Power-Efficient Applications. J. Low Power Electron. 10(3): 479-494 (2014) - [j25]Kamalika Datta, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
An Approach to Reversible Logic Synthesis Using Input and Output Permutations. Trans. Comput. Sci. 24: 92-110 (2014) - [j24]Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler:
Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic. Trans. Comput. Sci. 24: 129-146 (2014) - 2013
- [j23]Indrajit Pan, Ritwik Mukherjee, Hafizur Rahaman, Tuhina Samanta, Parthasarathi Dasgupta:
Optimization algorithms for the design of digital microfluidic biochips: A survey. Comput. Electr. Eng. 39(1): 112-121 (2013) - [j22]Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Derivation of test set for detecting multiple missing-gate faults in reversible circuits. Comput. Electr. Eng. 39(2): 225-236 (2013) - [j21]Nachiketa Das, Pranab Roy, Hafizur Rahaman:
Bridging fault detection in cluster based FPGA by using Muller C element. Comput. Electr. Eng. 39(8): 2469-2482 (2013) - [j20]Nachiketa Das, Pranab Roy, Hafizur Rahaman:
Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays. IET Comput. Digit. Tech. 7(5): 210-220 (2013) - [j19]Kamalika Datta, Indranil Sengupta, Hafizur Rahaman:
Particle Swarm Optimization Based Reversible Circuit Synthesis Using Mixed Control Toffoli Gates. J. Low Power Electron. 9(3): 363-372 (2013) - 2012
- [j18]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
Two-level clustering-based techniques for intelligent droplet routing in digital microfluidic biochips. Integr. 45(3): 316-330 (2012) - 2011
- [j17]Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya:
Fault diagnosis in reversible circuits under missing-gate fault model. Comput. Electr. Eng. 37(4): 475-485 (2011) - [j16]Jimson Mathew, Koushik Maharatna, Babita R. Jose, Hafizur Rahaman, Dhiraj K. Pradhan:
Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN. Circuits Syst. Signal Process. 30(4): 871-882 (2011) - [j15]Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques. J. Electron. Test. 27(5): 657-671 (2011) - [j14]Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Near-optimal Y-routed delay trees in nanometric interconnect design. IET Comput. Digit. Tech. 5(1): 36-48 (2011) - 2010
- [j13]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Secure Testable S-box Architecture for Cryptographic Hardware Implementation. Comput. J. 53(5): 581-591 (2010) - [j12]Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan:
A Galois field-based logic synthesis with testability. IET Comput. Digit. Tech. 4(4): 263-273 (2010) - [j11]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. IET Comput. Digit. Tech. 4(5): 428-437 (2010) - [j10]Somsubhra Talapatra, Hafizur Rahaman, Jimson Mathew:
Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 18(5): 847-852 (2010) - [j9]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Test Generation in Systolic Architecture for Multiplication Over GF(2 m). IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1366-1371 (2010) - 2009
- [j8]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Testable design of AND-EXOR logic networks with universal test sets. Comput. Electr. Eng. 35(5): 644-658 (2009) - [j7]Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan:
Single error correctable bit parallel multipliers over GF(2m). IET Comput. Digit. Tech. 3(3): 281-288 (2009) - 2008
- [j6]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir:
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008) - [j5]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. IEEE Trans. Instrum. Meas. 57(12): 2838-2845 (2008) - [j4]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir:
C-testable bit parallel multipliers over GF(2m). ACM Trans. Design Autom. Electr. Syst. 13(1): 5:1-5:18 (2008) - 2006
- [j3]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. J. Electron. Test. 22(2): 125-142 (2006) - [j2]Susmit Bagchi, Hafizur Rahaman, Purnendu Das:
MDVM System Concept, Paging Latency and Round-2 Randomized Leader Election Algorithm in SG. J. Adv. Comput. Intell. Intell. Informatics 10(5): 752-760 (2006) - 2002
- [j1]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. J. Comput. Sci. Technol. 17(6): 731-737 (2002)
Conference and Workshop Papers
- 2024
- [c209]Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman:
Parametric Fault Diagnosis of Analog Circuits using Adaptive Boosting. ISVLSI 2024: 717-720 - 2023
- [c208]Piyali Saha, Sudip Ghosh, Debajyoti Pal, Hafizur Rahaman:
Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC. IAIT 2023: 1:1-1:7 - [c207]Anchit Arun, Ananya Chakraborty, Priyanka Dutta, Debajyoti Pal, Tridibesh Nag, Debasis De, Sudip Ghosh, Hafizur Rahaman:
Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra. IAIT 2023: 23:1-23:6 - [c206]Pooja Joshi, Hafizur Rahaman:
A comprehensive review on ReRAM-based accelerators for deep learning. ISDCS 2023: 1-5 - [c205]Pooja Joshi, Hafizur Rahaman:
Memristor based In-Memory Computing for Edge AI Applications. ISDCS 2023: 1-6 - [c204]Rounak Roy, Sudip Ghosh, Hafizur Rahaman:
Implementation of Area Efficient Adders for Inexact Computing. ISDCS 2023: 1-4 - [c203]Santasri Giri Tunga, Subhajit Das, Sandip Bhattacharya, Hafizur Rahaman:
Electrothermal modeling of Multilayer Graphene Nanoribbon (MLGNR) Interconnect considering Energy-per-Layer Screening. ISDCS 2023: 1-4 - 2022
- [c202]Supriyo Srimani, Hafizur Rahaman:
Testing of Analog Circuits using Statistical and Machine Learning Techniques. ITC 2022: 619-626 - [c201]Bappaditya Mondal, Udit Narayana Kar, Chandan Bandyopadhyay, Debashri Roy, Hafizur Rahaman:
An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits. VDAT 2022: 249-261 - 2021
- [c200]Subhashree Basu, Malay Kule, Hafizur Rahaman:
Detection of Hardware Trojan in Presence of Sneak Path in Memristive Nanocrossbar Circuits. ISDCS 2021: 1-4 - [c199]Urbashi Basumata, Annapurna Mondal, Subhajit Das, Hafizur Rahaman:
Design of Two-Stage Fully-Differential Driver in SAR ADC with Indirect Feedback Compensation Technique. ISDCS 2021: 1-5 - [c198]Koustav Dey, Malay Kule, Hafizur Rahaman:
PUF Based Hardware Security: A Review. ISDCS 2021: 1-6 - [c197]Bramh Dev Singh, Sourav Naskar, Subhajit Das, Hafizur Rahaman:
Modelling, Analysis and Optimization of a 4th Order Delta-Sigma ADC and its Non-Idealities for Audio Codec Applications Achieving Dynamic Range Above 100dB. ISDCS 2021: 1-6 - [c196]Santasri Giri Tunga, Subhajit Das, Hafizur Rahaman:
A Brief Review of Recent Studies on Performance Improvement of Graphene Nanoribbon Interconnect. ISDCS 2021: 1-6 - [c195]Anirban Bhattacharjee, Hafizur Rahaman:
An Efficient 2D Mapping of Quantum Circuits to Nearest Neighbor Designs. iSES 2021: 53-58 - [c194]Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman:
Neural Network based Indirect Estimation of Functional Parameters of Amplifier by extracting features from Wavelet Transform. VLSID 2021: 310-315 - 2020
- [c193]Manas Kumar Parai, Kasturi Ghosh, Hafizur Rahaman:
Potentiality of Data Fusion in Analog Circuit Fault Diagnosis. ATS 2020: 1-6 - [c192]Debika Chaudhuri, Dalia Nandi Das, Hafizur Rahaman, Tamal Ghosh:
Modeling and Analysis of 3D IC Structures for Heat Mitigation by Thermal Through Silicon Vias. ICIIS 2020: 296-299 - [c191]Moumita Acharya, Soumyajit Poddar, Amlan Chakrabarti, Hafizur Rahaman:
Image Classification Based on Approximate Wavelet Transform and Transfer Learning on Deep Convolutional Neural Networks. ISDCS 2020: 1-6 - [c190]Laxmidhar Biswal, Khokan Mondal, Anirban Bhattacharjee, Hafizur Rahaman:
Fault-tolerant Quantum Implementation of Priority Encoder Circuit using Clifford+T-group. ISDCS 2020: 1-6 - [c189]Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs. ISDCS 2020: 1-6 - [c188]Debika Chaudhuri, Dalia Nandi Das, Hafizur Rahaman, Tamal Ghosh:
Heat Mitigation in 3D ICs by Improvised TTSV Structure. ISDCS 2020: 1-4 - [c187]Subhajit Das, Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman:
A Short Review on Graphene Nanoribbon Interconnect. ISDCS 2020: 1-7 - [c186]Soumajit Ghosh, Mitiko Miura-Mattausch, Takahiro Iizuka, Hideyuki Kikuchihara, Hafizur Rahaman, Hans Jürgen Mattausch:
History Effect on Circuit Performance of SOI-MOSFETs. ISDCS 2020: 1-5 - [c185]Sumit Kumar Jaiswal, Annapurna Mondal, Supriyo Srimani, Subhajit Das, Kasturi Ghosh, Hafizur Rahaman:
Design of a low power, high speed self calibrated dynamic latched comparator. ISDCS 2020: 1-6 - [c184]S. P. Kaarmukilan, Anakhi Hazarika, Amal Thomas K., Soumyajit Poddar, Hafizur Rahaman:
An Accelerated Prototype with Movidius Neural Compute Stick for Real-Time Object Detection. ISDCS 2020: 1-5 - [c183]Indranil Maity, Hafizur Rahaman, Partha Bhattacharyya:
DFT Based Simulation for Predicting Alcohol Adsorption on Oxygenated Functional Group Containing GO and rGO Based Gas Sensor Devices. ISDCS 2020: 1-6 - [c182]Joshua Roy Palathinkal, Yuvam Bhateja, Sudip Ghosh, Hafizur Rahaman:
A New Blind Invisible and Semi-Fragile Colour Image Watermarking Scheme in Spatial Domain. ISDCS 2020: 1-6 - [c181]Pranab Roy, Amiya Sahoo, Mriganka Chakrabarty, Hafizur Rahaman:
Microfluidic Cyberphysical Diagnostic System: An ANN Based Application. ISDCS 2020: 1-6 - [c180]Uttam Kumar Sahu, Ajoy Kumar Saha, Partha Sarathi Gupta, Hafizur Rahaman:
Valley Resolved Current Components Analysis of Monolayer TMDFETs. ISDCS 2020: 1-5 - [c179]Shivdeep, Sudip Ghosh, Hafizur Rahaman:
A New Digital Color Image Watermarking Algorithm with its FPGA and ASIC Implementation. ISDCS 2020: 1-6 - [c178]Subhashree Basu, Malay Kule, Hafizur Rahaman:
Symmetric Function Based Memristive Polimino PUF with Enhanced Security. iSES 2020: 143-146 - [c177]Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm. ISMVL 2020: 40-45 - [c176]Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Post Synthesis-Optimization of Reversible Circuit using Template Matching. VDAT 2020: 1-4 - 2019
- [c175]Sudip Poddar, Robert Wille, Hafizur Rahaman, Bhargab B. Bhattacharya:
Effect of Volumetric Split-Errors on Reactant-Concentration During Sample Preparation with Microfluidic Biochips. ACSS (2) 2019: 159-165 - [c174]Sagnik Bhar, Annapurna Mondal, Supriyo Srimani, Indranil Hatai, Subhajit Das, Kasturi Ghosh, Hafizur Rahaman:
A low power driver amplifier for Fully Differential ADC. ISDCS 2019: 1-6 - [c173]Ajay Kumar Chowdhary, Supriyo Srimani, Subhajit Das, Kasturi Ghosh, Hafizur Rahaman:
Estimation of non-linear effects for Capacitive DAC in SAR ADC: An Analytical Model. ISDCS 2019: 1-5 - [c172]Subhajit Das, Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman:
Comparative Stability Analysis of Pristine and AsF5 Intercalation Doped Top Contact Graphene Nano Ribbon Interconnects. ISDCS 2019: 1-4 - [c171]Soumajit Ghosh, Vishal Roshan, Avishek Dutta, Subhajit Das, Tapas Kumar Maiti, Mitiko Miura-Mattausch, Hafizur Rahaman:
Optimization of DC-DC Power Converter Design with Second Generation HiSIM_HV Model. ISDCS 2019: 1-5 - [c170]Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman:
Hardware Efficient Convolution Processing Unit for Deep Neural Networks. ISDCS 2019: 1-4 - [c169]Laxmidhar Biswal, Chandan Bandyopadhyay, Hafizur Rahaman:
Fault-tolerant Quantum Implementation of 1-bit and 4-bit Comparator Circuit using Clifford+T-group. ISED 2019: 1-6 - [c168]Laxmidhar Biswal, Chandan Bandyopadhyay, Hafizur Rahaman:
Efficient Implementation of Fault-Tolerant 4: 1 Quantum Multiplexer (QMUX) Using Clifford+T-Group. iSES 2019: 69-74 - [c167]Supriyo Srimani, Ravi Singh, Manas Kumar Parai, Kasturi Ghosh, Hafizur Rahaman:
Distortion Analysis Using Volterra Kernel for Amplifier Circuits. iSES 2019: 308-311 - [c166]Pampa Howladar, Pranab Roy, Hafizur Rahaman:
Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAs. ISVLSI 2019: 296-301 - [c165]Anakhi Hazarika, Avinash Jain, Soumyajit Poddar, Hafizur Rahaman:
Shift and Accumulate Convolution Processing Unit. TENCON 2019: 914-919 - [c164]Bappaditya Mondal, Anirban Bhattacharjee, Subham Saha, Shalini Parekh, Chandan Bandyopadhyay, Hafizur Rahaman:
An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit. VDAT 2019: 605-616 - [c163]Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits. VLSID 2019: 203-208 - [c162]Rakesh Das, Anupam Chattopadhyay, Hafizur Rahaman:
Optimizing Quantum Circuits for Modular Exponentiation. VLSID 2019: 407-412 - 2018
- [c161]Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Identification of Faulty TSV with a Built-In Self-Test Mechanism. ATS 2018: 1-6 - [c160]Sourav Ghosh, Hafizur Rahaman, Chandan Giri:
Test Diagnosis of Digital Microfluidic Biochips Using Image Segmentation. ATS 2018: 185-190 - [c159]Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits. ISVLSI 2018: 305-310 - [c158]Anirban Bhattacharjee, Chandan Bandyopadhyay, Laxmidhar Biswal, Hafizur Rahaman:
A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture. VDAT 2018: 593-605 - [c157]Laxmidhar Biswal, Anirban Bhattacharjee, Rakesh Das, Gopinath Thirunavukarasu, Hafizur Rahaman:
Quantum Domain Design of Clifford+T-Based Bidirectional Barrel Shifter. VDAT 2018: 606-618 - [c156]Arindam Sinharay, Subrata Das, Pranab Roy, Hafizur Rahaman:
An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon Circuit. VDAT 2018: 670-681 - [c155]Arindam Sinharay, Pranab Roy, Hafizur Rahaman:
Computing Fréchet Distance Metric Based L-Shape Tile Decomposition for E-Beam Lithography. VLSID 2018: 313-318 - [c154]Sourav Ghosh, Hafizur Rahaman, Chandan Giri:
Optimized Concurrent Testing of Digital Microfluidic Biochips. VLSID 2018: 453-454 - 2017
- [c153]Sudeep Ghosh, Surajit Kumar Roy, Hafizur Rahaman, Chandan Giri:
TSV repairing for 3D ICs using redundant TSV. ISED 2017: 1-5 - [c152]Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, Hafizur Rahaman:
All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer. ISED 2017: 1-5 - [c151]Bappaditya Mondal, Chandan Bandyopadhyay, Hafizur Rahaman:
Detection and localization of appearance faults in reversible circuits. ISED 2017: 1-5 - [c150]Soumyajit Poddar, Suraj, Amit Kumar Yadav, Hafizur Rahaman:
OTORNoC: Optical tree of rings network on chip for 1000 core systems. ISED 2017: 1-5 - [c149]Pranab Roy, Amiya Sahoo, Hafizur Rahaman:
Adaptive medical detection system: An iterative averaging method for automated detection analysis using DMFBs. ISED 2017: 1-6 - [c148]Arindam Sinharay, Pranab Roy, Hafizur Rahaman:
Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography. VDAT 2017: 287-295 - [c147]Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Modeling and Analysis of Transient Heat for 3D IC. VDAT 2017: 365-375 - [c146]Neha Chaudhuri, Chandan Bandyopadhyay, Hafizur Rahaman:
Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space. VDAT 2017: 421-426 - 2016
- [c145]Arko Dutt, Pranab Roy, Hafizur Rahaman:
TSV-aware 3-D IC structural planning with irregular die-size. APCCAS 2016: 713-716 - [c144]Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman:
Parametric Fault Detection in Analog Circuits: A Statistical Approach. ATS 2016: 275-280 - [c143]Anindita Chakraborty, Aparna Dhara, Hafizur Rahaman:
Design of memristor-based up-down counter using material implication logic. ICACCI 2016: 269-274 - [c142]Pampa Howladar, Debashri Roy, Pranab Roy, Hafizur Rahaman:
Cross-reference EWOD driving scheme and cross-contamination aware net placement technique for MEDA based DMFBs. ICACCI 2016: 614-619 - [c141]Pampa Howladar, Pranab Roy, Hafizur Rahaman:
An automated design of pin-constrained digital microfluidic biochip on MEDA architecture. ICACCI 2016: 1565-1570 - [c140]Chandan Bandyopadhyay, Shalini Parekh, Hafizur Rahaman:
A synthesis approach for ESOP-based reversible circuit. ICACCI 2016: 1741-1746 - [c139]Malay Kule, Avik Dutta, Hafizur Rahaman, Bhargab B. Bhattacharya:
High-speed decoder design using memristor-based nano-crossbar architecture. ISED 2016: 77-81 - [c138]Bappaditya Mondal, Chandan Bandyopadhyay, Hafizur Rahaman:
A testing scheme for mixed-control based reversible circuits. ISED 2016: 96-100 - [c137]Arindam Sinharay, Pranab Roy, Hafizur Rahaman:
VLSI thermal placement issues: A cooperative game theory based approach. ISED 2016: 106-111 - [c136]Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation. ISMVL 2016: 156-161 - [c135]Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman:
Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnects. VDAT 2016: 1-2 - [c134]Anindita Chakraborty, Rakesh Das, Chandan Bandyopadhyay, Hafizur Rahaman:
BDD based synthesis technique for design of high-speed memristor based circuits. VDAT 2016: 1-6 - [c133]Pranab Roy, Sudeshna Chakraborty, Hafizur Rahaman:
Synthesis aware sample preparation techniques using random sample sets in DMFB. VDAT 2016: 1-6 - [c132]Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. VLSID 2016: 573-574 - 2015
- [c131]Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das:
Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. DDECS 2015: 95-98 - [c130]Pranab Roy, Pampa Howladar, Raja Dastidar, Hafizur Rahaman, Parthasarathi Dasgupta:
3D integration in biochips: New proposed architectures for 3D applications in ATDA based digital microfluidic biochips. DTIS 2015: 1-6 - [c129]Surajit Kumar Roy, Kaustav Roy, Chandan Giri, Hafizur Rahaman:
Recovery of faulty TSVs in 3D ICs. ISQED 2015: 533-536 - [c128]Sudip Ghosh, Nachiketa Das, Subhajit Das, Santi Prasad Maity, Hafizur Rahaman:
An adaptive feedback based reversible watermarking algorithm using difference expansion. ReTIS 2015: 207-212 - [c127]Soumyajit Poddar, Prasun Ghosal, Hafizur Rahaman:
Adaptive CDMA based multicast method for photonic networks on chip. SoCC 2015: 298-303 - [c126]Suraj Gupta, Sabir Ali Mondal, Hafizur Rahaman:
Improved supply regulation and temperature compensated current reference circuit with low process variations. VDAT 2015: 1-6 - [c125]Surajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman:
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. VLSI-SoC 2015: 122-127 - [c124]Pratik Dutta, Chandan Bandyopadhyay, Hafizur Rahaman:
All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters. VLSID 2015: 232-237 - [c123]Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. VLSID 2015: 435-440 - 2014
- [c122]Kamalika Datta, Alhaad Gokhale, Indranil Sengupta, Hafizur Rahaman:
An ESOP-Based Reversible Circuit Synthesis Flow Using Simulated Annealing. ACSS (2) 2014: 131-144 - [c121]Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman:
Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method. ATS 2014: 68-73 - [c120]Sudip Ghosh, Nachiketa Das, Subhajit Das, Santi P. Maity, Hafizur Rahaman:
Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA. ICIT 2014: 123-128 - [c119]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips. DDECS 2014: 122-128 - [c118]Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
Optimizing DD-based synthesis of reversible circuits using negative control lines. DDECS 2014: 129-134 - [c117]Manjari Pradhan, Debesh K. Das, Chandan Giri, Hafizur Rahaman:
Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning. EWDTS 2014: 1-4 - [c116]Pranab Roy, Samadrita Bhattacharya, Hafizur Rahaman, Parthasarathi Dasgupta:
A new technique for layout based functional testing of modules in Digital Microfluidic Biochips. EWDTS 2014: 1-6 - [c115]Manodipan Sahoo, Hafizur Rahaman:
An ABCD parameter based modeling and analysis of crosstalk induced effects in Multilayer Graphene Nano Ribbon interconnects. ISCAS 2014: 1138-1142 - [c114]Pranab Roy, Aatreyi Bal, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
Automated two stage detection and analyzer system in multipartitioned Digital Microfluidic Biochips. ISCAS 2014: 1836-1840 - [c113]Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman:
A Novel GNR Interconnect Model to Reduce Crosstalk Delay. ISED 2014: 5-9 - [c112]Sudip Ghosh, Arijit Biswas, Santi P. Maity, Hafizur Rahaman:
Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA. ISED 2014: 68-72 - [c111]Pranab Roy, Tamosa Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
Multilevel Homogeneous Detection Analyzer for Medical Diagnostic Application in Digital Microfluidic Biochips. ISED 2014: 73-78 - [c110]Bappaditya Mondal, Chandan Bandyopadhyay, Dipak Kumar Kole, Jimson Mathew, Hafizur Rahaman:
Diagnosis of SMGF in ESOP Based Reversible Logic Circuit. ISED 2014: 89-93 - [c109]Manodipan Sahoo, Hafizur Rahaman:
Impact of Line Resistance Variations on Crosstalk Delay and Noise in Multilayer Graphene Nano Ribbon Interconnects. ISED 2014: 94-98 - [c108]Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler:
A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit. ISMVL 2014: 109-114 - [c107]Surajit Kumar Roy, Payel Ghosh, Hafizur Rahaman, Chandan Giri:
Session Based Core Test Scheduling for 3D SOCs. ISVLSI 2014: 196-201 - [c106]Pratik Dutta, Chandan Bandyopadhyay, Chandan Giri, Hafizur Rahaman:
Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder. ISVLSI 2014: 412-417 - [c105]Indrajit Das, Manodipan Sahoo, Pranab Roy, Hafizur Rahaman:
A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications. VDAT 2014: 1-6 - [c104]Pratik Dutta, Chandan Bandyopadhyay, Hafizur Rahaman:
All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit. VDAT 2014: 1-2 - [c103]Manodipan Sahoo, Prasun Ghosal, Hafizur Rahaman:
An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects. VLSID 2014: 433-438 - [c102]Pranab Roy, Samadrita Bhattacharya, Rupam Bhattacharyay, Firdousi Jamil Imam, Hafizur Rahaman, Parthasarathi Dasgupta:
A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips. VLSID 2014: 510-515 - 2013
- [c101]Manjari Pradhan, Chandan Giri, Hafizur Rahaman, Debesh K. Das:
Optimal stacking of SOCs in a 3D-SIC for post-bond testing. 3DIC 2013: 1-5 - [c100]Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri, Hafizur Rahaman:
Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. 3DIC 2013: 1-6 - [c99]Pranab Roy, Pampa Howladar, Rupam Bhattacharjee, Hafizur Rahaman, Parthasarathi Dasgupta:
A new cross contamination aware routing method with intelligent path exploration in digital microfluidic biochips. DTIS 2013: 50-55 - [c98]Kamalika Datta, Vishal Shrivastav, Indranil Sengupta, Hafizur Rahaman:
Reversible logic implementation of AES algorithm. DTIS 2013: 140-144 - [c97]Joyati Mondal, Debesh K. Das, Dipak Kumar Kole, Hafizur Rahaman:
A design for testability technique for quantum reversible circuits. EWDTS 2013: 1-4 - [c96]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya:
Reversible synthesis of symmetric boolean functions based on unate decomposition. ACM Great Lakes Symposium on VLSI 2013: 351-352 - [c95]Pranab Roy, Hafizur Rahaman, Partha Sarathi Gupta, Parthasarathi Dasgupta:
A new customized testing technique using a novel design of droplet motion detector for digital microfluidic Biochip systems. ICACCI 2013: 897-902 - [c94]Kamalika Datta, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
An evolutionary approach to reversible logic synthesis using output permutation. IDT 2013: 1-6 - [c93]Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs. IDT 2013: 1-3 - [c92]Pranab Roy, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
Novel designs of digital detection analyzer for intelligent detection and analysis in digital microfluidic biochips. IDT 2013: 1-6 - [c91]Surajit Kumar Roy, Joy Sankar Sengupta, Chandan Giri, Hafizur Rahaman:
Power constraints test scheduling of 3D stacked ICs. IDT 2013: 1-6 - [c90]Pranab Roy, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
Digital microfluidic system: A new design for heterogeneous sample based integration of multiple DMFBs. ISCAS 2013: 1905-1909 - [c89]Manodipan Sahoo, Hafizur Rahaman, Bhargab B. Bhattacharya:
Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects. ISED 2013: 16-20 - [c88]Chandan Bandyopadhyay, Debashri Roy, Dipak Kumar Kole, Kamalika Datta, Hafizur Rahaman:
ESOP-Based Synthesis of Reversible Circuit Using Improved Cube List. ISED 2013: 26-30 - [c87]Pranab Roy, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
An Intelligent Biochip System for Diagnostic Process Flow Based Integration of Combined Detection Analyzer. ISED 2013: 108-112 - [c86]Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
An Area and Power Efficient Dynamic TDMA Based Photonic Network on Chip. ISED 2013: 113-117 - [c85]Soumyajit Chatterjee, Hafizur Rahaman, Tuhina Samanta:
Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip. ISQED 2013: 252-256 - [c84]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler:
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. RC 2013: 182-195 - [c83]Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
Exploiting Negative Control Lines in the Optimization of Reversible Circuits. RC 2013: 209-220 - [c82]Joyati Mondal, Debesh Kumar Das, Dipak Kumar Kole, Hafizur Rahaman, Bhargab B. Bhattacharya:
On Designing Testable Reversible Circuits Using Gate Duplication. VDAT 2013: 322-329 - [c81]Pranab Roy, Samadrita Bhattacharya, Hafizur Rahaman, Parthasarathi Dasgupta:
A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips. VDAT 2013: 361-375 - 2012
- [c80]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta, Bhargab B. Bhattacharya:
A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips. Asian Test Symposium 2012: 25-30 - [c79]Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
On-Line Error Detection in Digital Microfluidic Biochips. Asian Test Symposium 2012: 332-337 - [c78]Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Automated path planning for washing in digital microfluidic biochips. CASE 2012: 115-120 - [c77]Pranab Roy, Rupam Bhattacharjee, Modud Sohid, Sudipta Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips. CODES+ISSS 2012: 423-432 - [c76]Prasun Ghosal, Sunita Choudhuri, Hafizur Rahaman:
Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach. HPCC-ICESS 2012: 532-537 - [c75]Debaprasad Das, Sourav Das, Hafizur Rahaman:
Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects. ISED 2012: 208-212 - [c74]Kamalika Datta, Indranil Sengupta, Hafizur Rahaman:
Particle Swarm Optimization Based Circuit Synthesis of Reversible Logic. ISED 2012: 226-230 - [c73]Manodipan Sahoo, Prasun Ghosal, Hafizur Rahaman:
Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube Interconnects. ISED 2012: 236-240 - [c72]Papia Manna, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization. ISED 2012: 246-250 - [c71]Pranab Roy, Moudud Sohid, Sudipta Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
System on Biochips: A New Design for Integration of Multiple DMFBs. ISED 2012: 256-260 - [c70]Sanga Chaki, Chandan Giri, Hafizur Rahaman:
Binary Difference Based Test Data Compression for NoC Based SoCs. ISVLSI 2012: 114-119 - [c69]Pranab Roy, Rupam Bhattacharjee, Hafizur Rahaman, Parthasarathi Dasgupta:
A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips. ISVLSI 2012: 320-325 - [c68]Pranab Roy, Sudipta Chakraborty, Moudud Sohid, Hafizur Rahaman, Parthasarathi Dasgupta:
A new digital analyzer for optically detected samples in Digital Microfluidic Biochips. MWSCAS 2012: 462-465 - [c67]Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Partitioning-based wirelength estimation technique for Y-routing. SBCCI 2012: 1-6 - [c66]Tuhina Samanta, Raka Sardar, Hafizur Rahaman, Parthasarathi Dasgupta, Bhargab B. Bhattacharya:
A heuristic method for obstacle avoiding group Steiner tree construction. SLIP 2012: 21 - [c65]Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
Design of an NoC with on-chip photonic interconnects using adaptive CDMA links. SoCC 2012: 352-357 - [c64]Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahaman:
Post-bond Stack Testing for 3D Stacked IC. VDAT 2012: 59-68 - [c63]Debaprasad Das, Avishek Sinha Roy, Hafizur Rahaman:
Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors. VDAT 2012: 233-242 - [c62]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. VDAT 2012: 258-269 - [c61]Debaprasad Das, Hafizur Rahaman:
Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects. VDAT 2012: 289-299 - [c60]Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman, Santi P. Maity:
VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark. VDAT 2012: 375-376 - [c59]Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
A Photonic Network on Chip with CDMA Links. VDAT 2012: 377-378 - [c58]Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman, Parthasarathi Dasgupta:
Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor. VDAT 2012: 379-380 - [c57]Ritwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, Parthasarathi Dasgupta:
A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip. VLSI Design 2012: 227-232 - [c56]Kamalika Datta, Gaurav Rathi, Indranil Sengupta, Hafizur Rahaman:
Synthesis of Reversible Circuits Using Heuristic Search Method. VLSI Design 2012: 328-333 - 2011
- [c55]Indrajit Banerjee, Prasenjit Chanak, Biplab Kumar Sikdar, Hafizur Rahaman:
DFDNM: A Distributed Fault Detection and Node Management Scheme for Wireless Sensor Network. ACC (3) 2011: 68-81 - [c54]Prasun Ghosal, Hafizur Rahaman, Satrajit Das, Arindam Das, Parthasarathi Dasgupta:
Obstacle Aware Routing in 3D Integrated Circuits. ADCONS 2011: 451-460 - [c53]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
A Multi-pin Droplet Routing Algorithm for Digital Microfluidic Biochips. BIODEVICES 2011: 216-223 - [c52]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2011: 229-234 - [c51]Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
On residue removal in digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2011: 391-394 - [c50]Indrajit Banerjee, Prasenjit Chanak, Hafizur Rahaman:
SBFDR: Sector Based Fault Detection and Recovery in Wireless Sensor Networks. HPAGC 2011: 461-469 - [c49]Nachiketa Das, Pranab Roy, Hafizur Rahaman:
Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application. ISED 2011: 146-151 - [c48]Pranab Roy, Hafizur Rahaman, Rupam Bhattacharya, Parthasarathi Dasgupta:
A Best Path Selection Based Parallel Router for DMFBs. ISED 2011: 176-181 - [c47]Debaprasad Das, Hafizur Rahaman:
Crosstalk and Gate Oxide Reliability Analysis in Graphene Nanoribbon Interconnects. ISED 2011: 182-187 - [c46]Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman:
Optimization of Test Wrapper for TSV Based 3D SOCs. ISED 2011: 188-193 - [c45]Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits. ISED 2011: 200-205 - [c44]Indrajit Pan, Parthasarathi Dasgupta, Hafizur Rahaman, Tuhina Samanta:
Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip. ISED 2011: 223-229 - [c43]Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman:
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. ISED 2011: 230-235 - [c42]Tuhina Samanta, Sanoara Khatun, Hafizur Rahaman, Parthasarathi Dasgupta:
Crosstalk aware coupled line delay tree construction for on-chip interconnects. ISQED 2011: 353-358 - [c41]Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman:
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs. ISVLSI 2011: 31-36 - [c40]Pranab Roy, Rajesh Mandal, Hafizur Rahaman, Parthasarathi Dasgupta:
A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips. ISVLSI 2011: 317-318 - [c39]Indrajit Banerjee, Prasenjit Chanak, Anirban Datta, Hafizur Rahaman:
DJSS: Distributed job scheduling scheme for WSN. ReTIS 2011: 145-150 - 2010
- [c38]Goutam Mali, Suman Das, Hafizur Rahaman, Chandan Giri:
Non-preemptive test scheduling for Network-on-Chip(NoC) based systems by reusing NoC as TAM. APCCAS 2010: 268-271 - [c37]Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. Asian Test Symposium 2010: 33-38 - [c36]Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem. Asian Test Symposium 2010: 111-116 - [c35]Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
Minimizing Thermal Disparities during Placement in 3D ICs. CSE 2010: 160-167 - [c34]Somsubhra Talapatra, Hafizur Rahaman, Samir K. Saha:
Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m). DSD 2010: 427-432 - [c33]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
A novel droplet routing algorithm for digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2010: 441-446 - [c32]Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan:
On the design of different concurrent EDC schemes for S-Box and GF(p). ISQED 2010: 211-218 - [c31]Indrajit Banerjee, Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar, Mamata Dalui:
SSMCA: CA based Segmented Sensor Network Management scheme. SMC 2010: 177-184 - [c30]Somsubhra Talapatra, Hafizur Rahaman:
Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(pm). VLSI-SoC 2010: 219-224 - [c29]Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir:
On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291 - 2009
- [c28]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
C-testable S-box implementation for secure advanced encryption standard. IOLTS 2009: 210-211 - [c27]Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta:
A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. VLSI Design 2009: 387-392 - 2008
- [c26]Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Bhargab B. Bhattacharya, D. Dutta Majumder, Krishnendu Chakrabarty:
Accelerated Functional Testing of Digital Microfluidic Biochips. ATS 2008: 295-300 - [c25]Indrajit Banerjee, Hafizur Rahaman:
UDDN: Unidirectional Data Dissemination via Negotiation. ICOIN 2008: 1-5 - [c24]Nachiketa Das, Pranab Roy, Hafizur Rahaman:
On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element. IOLTS 2008: 190-191 - [c23]Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. ISVLSI 2008: 369-374 - [c22]Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
Revisiting fidelity: a case of elmore-based Y-routing trees. SLIP 2008: 27-34 - [c21]Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan:
Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38 - [c20]Hafizur Rahaman, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya:
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. VLSI Design 2008: 163-168 - [c19]Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan:
Design of Reversible Finite Field Arithmetic Circuits with Error Detection. VLSI Design 2008: 453-459 - [c18]Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634 - 2007
- [c17]Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya:
Optimum Test Set for Bridging Fault Detection in Reversible Circuits. ATS 2007: 125-128 - [c16]Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan:
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208 - [c15]Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
Minimum-Congestion Placement for Y-interconnects: Some studies and observations. ISVLSI 2007: 73-80 - [c14]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484 - [c13]Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan:
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430 - 2006
- [c12]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). HLDVT 2006: 48-54 - [c11]Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI. ISCAS 2006 - [c10]Indrajit Banerjee, Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar:
An Energy Effilcient Monitoring of Ad-Hoc Sensor Network with Cellular Automata. SMC 2006: 5100-5105 - 2005
- [c9]Hafizur Rahaman, Debesh K. Das:
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. ASP-DAC 2005: 172-177 - [c8]Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar:
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. Asian Test Symposium 2005: 284-287 - [c7]Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design. IICAI 2005: 232-251 - 2004
- [c6]Hafizur Rahaman, Debesh K. Das:
A Simple Delay Testable Synthesis of Symmetric Functions. AACC 2004: 263-270 - [c5]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. ASP-DAC 2004: 224-229 - [c4]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. VLSI Design 2004: 487-492 - 2003
- [c3]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. Asian Test Symposium 2003: 284-289 - 2002
- [c2]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
A New Synthesis of Symmetric Functions. ASP-DAC/VLSI Design 2002: 160-165 - 1999
- [c1]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. ASP-DAC 1999: 287-
Editorship
- 2017
- [e2]Iain Phillips, Hafizur Rahaman:
Reversible Computation - 9th International Conference, RC 2017, Kolkata, India, July 6-7, 2017, Proceedings. Lecture Notes in Computer Science 10301, Springer 2017, ISBN 978-3-319-59935-9 [contents] - 2012
- [e1]Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay:
Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings. Lecture Notes in Computer Science 7373, Springer 2012, ISBN 978-3-642-31493-3 [contents]
Informal and Other Publications
- 2019
- [i3]Sudip Poddar, Robert Wille, Hafizur Rahaman, Bhargab B. Bhattacharya:
Dilution with Digital Microfluidic Biochips: How Unbalanced Splits Corrupt Target-Concentration. CoRR abs/1901.00353 (2019) - [i2]Laxmidhar Biswal, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Hafizur Rahaman:
New techniques for fault-tolerant decomposition of Multi-Controlled Toffoli gate. CoRR abs/1904.06920 (2019) - 2011
- [i1]Indrajit Banerjee, Prasenjit Chanak, Hafizur Rahaman:
CCABC: Cyclic Cellular Automata Based Clustering For Energy Conservation in Sensor Networks. CoRR abs/1109.2430 (2011)
Coauthor Index
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