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ORCIDSoCC 2012: Niagara Falls, NY, USA
- Ramalingam Sridhar, Norbert Schuhmann, Kaijian Shi:
IEEE 25th International SOC Conference, SOCC 2012, Niagara Falls, NY, USA, September 12-14, 2012. IEEE 2012, ISBN 978-1-4673-1294-3 - Bernard S. Meyerson:
Keynote speaker: Driving innovation in the "post-silicon" world. 1-2 - Richard Grisenthwaite:
Plenary speaker: Low power solutions for a smarter future. 3 - Raj Yavatkar:
Plenary speaker: Era of SoCs: What is next? 4 - Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang:
An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. 5-10 - Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa:
An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. 11-14 - Sebastian M. Londono, José Pineda de Gyvez:
A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. 15-20 - Na Gong, Shixiong Jiang, Anoosha Challapalli, Manpinder Panesar, Ramalingam Sridhar:
Variation-and-aging aware low power embedded SRAM for multimedia applications. 21-26 - Tolga Soyata
, John C. Liobe:
pbCAM: Probabilistically-banked Content Addressable Memory. 27-32 - Yuejian Wu, Sandy Thomson, Han Sun, David Krause, Song Yu, George Kurio:
"Free" Razor: A novel adaptive voltage scaling low power technique for data path SoC designs. 33-38 - Bo Jiang, Tian Xia:
ADPLL variables determinations based on phase noise, spur and locking time. 39-44 - Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdelsalam, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor:
A novel digital loop filter architecture for bang-bang ADPLL. 45-50 - Lampros Mountrichas, Theodore Laopoulos, Stilianos Siskos:
A 1.7GS/s 6-bit Flash A/D converter with distributed offset cancelling sample-and-hold. 51-56 - Jin-Cheol Seo, Sang-Soon Im, Kwan-Hee Yoon, Seung-Wook Oh, Taek-Joon An, Gi-Yeol Bae, Jin-Ku Kang:
A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. 57-60 - Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito:
Gray-level image recognition on a dynamically reconfigurable vision architecture. 61-65 - Tahseen Shakir, Manoj Sachdev:
A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs. 66-71 - Omar Haridy, Harish Krishnamurthy, Amr Helmy, Yehea Ismail:
Synthesizable delay line architectures for digitally controlled voltage regulators. 72-77 - Chun-Ming Huang, Chih-Chyau Yang, Chien-Ming Wu, Chun-Chieh Chiu, Yi-Jun Liu, Chun-Chieh Chu, Nien-Hsiang Chang, Wen-Ching Chen, Chih-Hsing Lin, Hua-Hsin Luo:
A novel design flow for a 3D heterogeneous system prototyping platform. 78-82 - Edin Kadric, Naraig Manjikian, Zeljko Zilic:
An FPGA implementation for a high-speed optical link with a PCIe interface. 83-87 - Andrew Marshall:
Invited talk: Noise and mismatch in sub 28nm silicon processes. 88-93 - Matthew Catanzaro, Dhireesha Kudithipudi:
Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement. 94-99 - Aveek Dutta, Sanjiv Sambandan:
Limitations of integrating field induced aggregation based fault repair automatons with integrated circuits. 100-103 - Stefan Hoelldampf, Hyun-Sek Lukas Lee, Daniel Zaum, Markus Olbrich, Erich Barke:
Efficient generation of analog circuit models for accelerated mixed-signal simulation. 104-109 - Susie Kim, Seung-In Na, Tae-Hoon Kim, Hyunjoong Lee, Sunkwon Kim, Cyuyeol Rhee, Suhwan Kim:
Neural recording system with low-noise analog front-end and comparator-based cyclic ADC. 110-114 - Zhihua Gan, Emre Salman, Milutin Stanacevic:
Methodology to determine dominant noise source in a system-on-chip based implantable device. 115-119 - Jun Zhang, Huihua Liu:
A wide tuning range QCCO based on CMOS active inductors. 120-124 - Sergio Gómez, Francesc Moll:
Evaluation of layout design styles using a quality design metric. 125-130 - Cory E. Merkel, Dhireesha Kudithipudi, Andres Kwasinski:
Lightweight energy prediction framework for solar-powered wireless sensor networks. 131-136 - Mehdi Sadi, Mircea Stan:
Design of near threshold All Digital Delay Locked Loops. 137-142 - Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii:
A stable chip-ID generating physical uncloneable function using random address errors in SRAM. 143-147 - Ravi Patel, Engin Ipek, Eby G. Friedman:
STT-MRAM memory cells with enhanced on/off ratio. 148-152 - Hamed Sajjadi Kia, Cristinel Ababei:
Efficient high-speed current-mode links for network-on-chip performance optimization. 153-158 - Li Zheng, Muhannad S. Bakir:
Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer. 159-164 - Jiangjiang Liu, Jianyong Zhang:
Interconnect compression and its benefits for multi-core systems. 165-170 - Young-Jin Yoon, Nicola Concer, Luca P. Carloni:
Ventti: A vertically integrated framework for simulation and optimization of networks-on-Chip. 171-176 - Alexander Mykyta, Dorin Patru, Eli Saber, Gene Roylance, Brad Larson:
Reconfigurable framework for high-bandwidth stream-oriented data processing. 177-183 - Gang Wang, Jian Wang, Zi-Chu Qi:
A testability-aware low power architecture. 184-189 - Robert E. Geer:
Plenary speaker: Connectivity driven systems: On-chip, off-chip and in-between. 190-191 - Josef Dobes, Jan Míchal, Viera Biolková:
Multi-objective optimization of radio-frequency front-ends. 192-197 - Shanthi Sudalaiyandi, Tuan Anh Vu, Håkon A. Hjortland, Øivind Næss, Tor Sverre Lande:
Continuous-time single-symbol IR-UWB symbol detection. 198-201 - Ciaran Toal, Sakir Sezer, Dwayne Burns, Pei Xiao, Vincent F. Fusco:
A 1Gbps FPGA-based wireless baseband MIMO transceiver. 202-207 - Xin Yang, Sakir Sezer:
Implementation of a network flow lookup circuit for next-generation packet classifiers. 208-212 - Goran Panic, Thomas Basmer, Schomann Henry, Steffen Peter, Frank Vater, Klaus Tittelbach-Helmrich:
Design of a sensor node crypto processor for IEEE 802.15.4 applications. 213-217 - Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. 218-223 - Yuan Ren, Michael Gansen, Tobias G. Noll:
Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme. 224-229 - Stefanos Kaxiras, Alberto Ros:
Efficient, snoopless, System-on-Chip coherence. 230-235 - Amal Fahad, Tolga Soyata, Tai Wang, Gaurav Sharma, Wendi B. Heinzelman, Kai Shen:
SOLARCAP: Super capacitor buffering of solar energy for self-sustainable field systems. 236-241 - Upasna Vishnoi, Michael Meixner, Tobias G. Noll:
An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks. 242-247 - Gustavo A. Patiño-Álvarez, Jorge González, Jiang Chau Wang, Marius Strum:
Workload and task characterization based on operation modes timing analysis. 248-253 - Jin-Tai Yan, Zhi-Wei Chen:
Direction-constrained layer assignment for rectangle escape routing. 254-259 - Ahmed Arafa, Hend Wagieh, Rami Fathy Salem, John Ferguson, Doug Morgan, Mohab H. Anis, Mohamed Dessouky:
Schematic-driven physical verification: Fully automated solution for analog IC design. 260-264 - Christopher Ryan, Kris Monsen, Scott Smith, Henry So:
Multi-Clock DFT architecture for interface characterization and power. 265-270 - Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Optimal power-constrained SoC test schedules with customizable clock rates. 271-276 - Johannes Grinschgl, Armin Krieg, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
Efficient fault emulation using automatic pre-injection memory access analysis. 277-282 - Tao Xie, Wolfgang Müller, Florian Letombe:
Mutation-analysis driven functional verification of a soft microprocessor. 283-288 - Susmita Sur-Kolay:
Intellectual property protection and security of SoCs - An embedded tutorial. 289 - Yiran Chen, Qing Wu:
Neuromorphic computing: A SoC scaling path for the next decades. 290-291 - Garrett S. Rose:
Exploiting memristive device behavior for emerging digital logic and memory applications. 292 - Qinru Qiu:
A massive parallel neuromorphic computing model for intelligent text recognition. 293 - Hai Li:
Memristor in neuromorphic computing. 294 - M. Binesh Marvasti, Ted H. Szymanski:
A power-area analysis of NoCs in FPGAs. 295-300 - Jacob Murray, Partha Pratim Pande, Behrooz A. Shirazi:
DVFS-enabled sustainable wireless NoC architecture. 301-306 - Suhas M. Satheesh, Emre Salman:
Design space exploration for robust power delivery in TSV based 3-D systems-on-chip. 307-311 - Tian Xia, Guoan Wang:
A scalable electrical characterization method for inter-strata interconnects in 3-D ICs. 312-316 - Hsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, Huang-Lun Lin:
Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC. 317-321 - Yu-Hung Cho, Ing-Chao Lin, Yi-Ming Yang:
Aging-aware reliable multiplier design. 322-327 - Yongtae Kim, Yong Zhang, Peng Li:
A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning. 328-333 - Hang Yin, Weitao Du, Yu Hen Hu, Rui Lv:
A novel flexible foldable systolic architecture FIR filters generator. 334-339 - Davide Zoni, William Fornaciari:
A sensor-less NBTI mitigation methodology for NoC architectures. 340-345 - Dan Zhao, Yi Wang:
Design of a scalable RF microarchitecture for heterogeneous MPSoCs. 346-351 - Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
Design of an NoC with on-chip photonic interconnects using adaptive CDMA links. 352-357 - Ye Lu, Changlin Chen, John V. McCanny, Sakir Sezer:
Design of interlock-free combined allocators for Networks-on-Chip. 358-363 - Eduardo Weber Wächter, Fernando Gehm Moraes:
MAZENOC: Novel approach for fault-tolerant NOC routing. 364-369 - Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang:
On-chip self-calibrated process-temperature sensor for TSV 3D integration. 370-375 - Tamer Ragheb, Andrew Marshall:
Calibration of propagation delay of flip-flops. 376-380 - Bi-Ting Lai, Tai-Hung Li, Tai-Chen Chen:
Native-conflict-avoiding track routing for double patterning technology. 381-386 - Jordi Perez-Puigdemont, Antonio Calomarde, Francesc Moll:
Variation tolerant self-adaptive clock generation architecture based on a ring oscillator. 387-392
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