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"Optimizing test time for core-based 3-d integrated circuits by a technique ..."

Manjari Pradhan et al. (2014)

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DOI: 10.1109/EWDTS.2014.7027044

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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  dblp key:
  - conf/ewdts/PradhanDGR14
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  persistent URL:
  - https://dblp.org/rec/conf/ewdts/PradhanDGR14
Manjari Pradhan, Debesh K. Das, Chandan Giri, Hafizur Rahaman:
Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning. EWDTS 2014: 1-4

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