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ORCIDIEEE Journal of Solid-State Circuits, Volume 37
Volume 37, Number 1, January 2002
- Omid Oliaei, Patrick Clément, Philippe Gorisse:
A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE. 2-10 - Tai-Haur Kuo, Kuan-Dar Chen, Horng-Ru Yeng:
A wideband CMOS sigma-delta modulator with incremental data weighted averaging. 11-17 - Daniel R. McMahill, Charles G. Sodini:
A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer. 18-26 - Hussain A. Alzaher, Hassan O. Elwan, Mohammed Ismail:
A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers. 27-37 - Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino:
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. 38-50 - Oscal T.-C. Chen, Robin Ruey-Bin Sheen:
A power-efficient wide-range phase-locked loop. 51-62 - Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang:
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. 63-76 - Snezana Jenei, Bart K. J. C. Nauwelaers, Stefaan Decoutere:
Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors. 77-80 - Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, T. R. Viswanathan:
A CMOS bandgap reference without resistors. 81-83 - Toru Tanzawa
, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura:
Circuit techniques for a 1.8-V-only NAND flash memory. 84-89 - Amr M. Fahim, Mohamed I. Elmasry:
Low-power high-performance arithmetic circuits and architectures. 90-94 - Ming-Hwa Sheu, Su-Hon Lin:
Fast compensative design approach for the approximate squaring function. 95-97
Volume 37, Number 2, February 2002
- Bernhard E. Boser:
Editorial. 103 - Bernhard E. Boser:
New associate editor. 104 - Michael Q. Le, Paul J. Hurst, John P. Keane:
An adaptive analog noise-predictive decision-feedback equalizer. 105-113 - Pietro Andreani, Sven Mattisson:
On the use of Nauta's transconductor in low-frequency CMOS gm-C bandpass filters. 114-124 - Bogdan Pankiewicz, Marek Wójcikowski, Stanislaw Szczepanski, Yichuang Sun:
A field programmable analog array for CMOS continuous-time OTA-C filter applications. 125-136 - Koen L. R. Mertens, Michiel S. J. Steyaert:
A 700-MHz 1-W fully differential CMOS class-E power amplifier. 137-141 - Philippe Maige, Yannick Guédon:
A class-D vertical booster for CRT. 142-150 - Zoran B. Randjelovic, Maher Kayal, Radevoje Popovic, Hubert Blanchard:
Highly sensitive Hall magnetic sensor microsystem in CMOS technology. 151-159 - Massimo Barbaro, Pierre-Yves Burgi, Alessandro Mortara, Pascal Nussbaum, Friedrich Heitger:
A 100×100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding. 160-172 - Dirk Droste, Josef Bille:
An ASIC for Hartmann-Shack wavefront detection. 173-182 - Keith A. Bowman, Steven G. Duvall, James D. Meindl:
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. 183-190 - Se-Joong Lee, Hoi-Jun Yoo:
Race logic architecture (RALA): a novel logic concept using the race scheme of input variables. 191-201 - David J. Kinniment, Alexandre V. Bystrov, Alex Yakovlev:
Synchronization circuit performance. 202-209 - Masayuki Miyazaki, Goichi Ono, Koichiro Ishibashi:
A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. 210-217 - Hans Jürgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide:
Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. 218-227 - Samuel A. Steidl, John F. McDonald:
A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology. 228-236 - Seong-Mo Yim, Tong Chen, Kenneth K. O:
The effects of a ground shield on the characteristics and performance of spiral inductors. 237-244 - Jae-Yoon Sim, Jang-Jin Nam, Young-Soo Sohn, Hong-June Park, Chang-Hyun Kim, Soo-In Cho:
A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. 245-250 - Jae-Kyung Wee, Kyeong-Sik Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, Jong-Doo Joo, Jin-Yong Chung:
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. 251-254 - Bendik Kleveland, Carlos H. Diaz, Dieter Vook, Liam Madden, Thomas H. Lee, S. Simon Wong:
Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design". 255
Volume 37, Number 3, March 2002
- Jorge Grilo, Ian Galton, Kevin J. Wang, Raymond Montemayor:
A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. 271-278 - Ovidiu Bajdechi, Johan H. Huijsing:
A 1.8-V ΔΣ modulator interface for an electret microphone with on-chip reference. 279-285 - Troy Stockstad, Hirokazu Yoshizawa:
A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier. 286-292 - Troy Stockstad, Hirokazu Yoshizawa:
A 40-μA/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implants. 293-301 - Iuri Mehr, Prabir C. Maulik, Donald Paterson:
A 12-bit integrated analog front end for broadband wireline networks. 302-309 - David J. Foley, Michael P. Flynn:
A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS. 310-316 - Kamran Azadet, Erich F. Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Michael Shaffer, Leilei Song, Meng-Lin Yu:
Equalization and FEC techniques for optical transceivers. 317-327 - Bernd-Ulrich H. Klepser, Markus Scholz, Edmund Götz:
A 10-GHz SiGe BiCMOS phase-locked-loop frequency synthesizer. 328-335 - Anne Spataro, Yann Deval, Jean-Baptiste Bégueret, Pascal Fouillat:
A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer. 336-341 - Pietro Andreani, Henrik Sjöland:
Tail current noise suppression in RF CMOS VCOs. 342-348 - Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz:
Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation. 349-356 - Atsushi Yoshizawa, Yannis P. Tsividis:
Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers. 357-364 - Uma Chilakapati, Terri S. Fiez, Aria Eshraghi:
A CMOS transconductor with 80-dB SFDR up to 10 MHz. 365-370 - Ichiro Aoki, Scott D. Kee, David B. Rutledge, Ali Hajimiri:
Fully integrated CMOS power amplifier design using the distributed active-transformer architecture. 371-383 - Roberto Aparicio, Ali Hajimiri:
Capacity limits and matching properties of integrated capacitors. 384-393 - Hasnain Lakdawala, Xu Zhu, Hao Luo, Suresh Santhanam, L. Richard Carley, Gary K. Fedder:
Micromachined high-Q inductors in a 0.18-μm copper interconnect low-k dielectric CMOS process. 394-403 - Andrew J. Blanksby, Chris J. Howland:
A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder. 404-412 - Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai:
VTH-hopping scheme to reduce subthreshold leakage for low-power processors. 413-419 - W. Rhett Davis, Ning Zhang, Kevin Camera, Dejan Markovic, Tina Smilkstein, M. Josie Ammer, Engling Yeo, Stephanie Augsburger, Borivoje Nikolic, Robert W. Brodersen:
A design environment for high-throughput low-power dedicated signal processing systems. 420-431 - Conor Donovan, Michael P. Flynn:
A "digital" 6-bit ADC in 0.25-μm CMOS. 432-437 - Johan D. van der Tang, Dieter Kasperkovitz, Arthur H. M. van Roermund:
A 9.8-11.5-GHz quadrature ring oscillator for optical receivers. 438-442 - Salvatore Cosentino, Pietro Filoramo, Angelo Granata, Marco Marletta, Giuseppe Martino, Roberto Pelleriti, Felice Torrisi, Mario Paparo, Gaetano Cosentino, Piero Vita, Giuseppe Palmisano:
An integrated RF transceiver for DECT application. 443-449 - Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuya Matsumura:
A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. 450-454
Volume 37, Number 4, April 2002
- Chi-Wa Lo, Howard Cam Luong:
A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications. 459-470 - Chih-Chun Tang, Chia-Hsin Wu, Shen-Iuan Liu:
Miniature 3-D inductors in standard CMOS process. 471-480 - Frank Ellinger, Rolf Vogt, Werner Bächtold:
Ultracompact reflective-type phase shifter MMIC at C-band with 360° phase-control range for smart antenna combining. 481-486 - Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura:
A low-impedance open-bitline array for multigigabit DRAM. 487-498 - Mohamed M. Hafed, Nazmy Abaskharoun, Gordon W. Roberts:
A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits. 499-514 - Woogeun Rhee, Biagio Bisanti, Akbar Ali:
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution. 515-520 - Chih-Ming Hung, Kenneth K. O:
A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop. 521-525 - Ka Nang Leung, Philip K. T. Mok:
A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device. 526-530
Volume 37, Number 5, May 2002
- Masakazu Yamashina, Shekhar Y. Borkar:
Guest editorial. 535 - Yido Koo, Hyungki Huh, Yongsik Cho, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems. 536-542 - Brian A. Floyd, Chih-Ming Hung, Kenneth K. O:
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. 543-552 - Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura:
A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range. 553-558 - Shiro Dosho, Takashi Morie, Hirokuni Fujiyama:
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process. 559-565 - Ayman Shabra, Hae-Seung Lee:
Oversampled pipeline A/D converters with mismatch shaping. 566-578 - Theerachet Soorapanth, S. Simon Wong:
A 0-dB IL 2140±30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS. 579-586 - Daisaburo Takashima, Hiroaki Nakano:
A cell transistor scalable DRAM array architecture. 587-591 - Shoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki:
Bitline GND sensing technique for low-voltage operation FeRAM. 592-598 - Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi:
A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. 599-604 - Mitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda:
A 63-μW standby power microcontroller with on-chip hybrid regulator scheme. 605-611 - Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo:
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. 612-623 - Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. 624-632 - Atila Alvandpour, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A sub-130-nm conditional keeper technique. 633-638 - Jaeha Kim, Mark A. Horowitz:
An efficient digital sliding controller for adaptive power-supply regulation. 639-647 - Chulwoo Kim, Sung-Mo Kang:
A low-swing clock double-edge triggered flip-flop. 648-652 - Peter J. Vancorenland, Michiel S. J. Steyaert:
A 1.57-GHz fully integrated very low-phase-noise quadrature VCO. 653-656 - Johan van der Tang, Pepijn van de Ven, Dieter Kasperkovitz, Arthur H. M. van Roermund:
Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator. 657-661 - Shahram Mahdavi, Asad A. Abidi:
Fully integrated 2.2-mW CMOS front end for a 900-MHz wireless receiver. 662-669
Volume 37, Number 6, June 2002
- Shang-Yuan (Sean) Chuang, Terry L. Sculley:
A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. 674-683 - Alireza Shirvani, David K. Su, Bruce A. Wooley:
A CMOS RF power amplifier with parallel amplification for efficient power control. 684-693 - Ming-Chou Chiang, Shey-Shi Lu, Chin-Chun Meng, Shih-An Yu, Shih-Cheng Yang, Yi-Jen Chan:
Analysis, design, and optimization of InGaP-GaAs HBT matched-impedance wide-band amplifiers with multiple feedback loops. 694-701 - Sander L. J. Gierkink, Ed van Tuijl:
A coupled sawtooth oscillator combining low jitter with high control linearity. 702-710 - Xavier Maillard, Frédéric Devisch, Maarten Kuijk:
A 900-Mb/s CMOS data recovery DLL using half-frequency clock. 711-715 - Bendik Kleveland, Xiaoning Qi, Liam Madden, Takeshi Furusawa, Robert W. Dutton, Mark A. Horowitz, S. Simon Wong:
High-frequency characterization of on-chip digital interconnects. 716-725 - Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung:
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. 726-734 - Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe:
A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell. 735-750 - Douglas J. Fouts, Phillip E. Pace, Christopher Karow, Stig R. T. Ekestorm:
A single-chip false target radar image generator for countering wideband imaging radars. 751-759 - Paul Leroux, Johan Janssens, Michiel Steyaert:
A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver]. 760-765 - Kalle Kivekäs, Aarno Pärssinen, Jussi Ryynänen, Jarkko Jussila, Kari Halonen:
Calibration techniques of active BiCMOS mixers. 766-769 - Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez:
Transconductance amplifier structures with very small transconductances: a comparative design approach. 770-775 - Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez:
A CMOS transconductance amplifier architecture with wide tuning range for very low frequency applications. 776-781
Volume 37, Number 7, July 2002
- Christian C. Enz, Stefan Rusu:
Guest editorial. 795-797 - Teemu Salo, Saska Lindfors, Kari A. I. Halonen:
A 80-MHz bandpass ΔΣ modulator for a 100-MHz IF receiver. 798-808 - Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura:
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. 809-816 - Mustafa Keskin, Un-Ku Moon, Gabor C. Temes:
A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps. 817-824 - Marzia Annovazzi, Vittorio Colonna, Gabriele Gandolfi, Fabrizio Stefani, Andrea Baschirotto:
A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology. 825-834 - Bram De Muer, Michel S. J. Steyaert:
A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800. 835-844 - Peter R. Kinget, Robert C. Melville, David E. Long, Venugopal Gopinathan:
An injection-locking scheme for precision quadrature generation. 845-851 - Ryuichi Fujimoto, Kenji Kojima, Shoji Otaka:
A 7-GHz 1.8-dB NF CMOS low-noise amplifier. 852-856 - Hubert Weinberger, Andreas Wiesbauer, Christian Fleischhacker, Joerg Hauptmann, Thomas Ferianz, Michael Staber, Dietmar Sträußnigg, Berthold Seger:
An ADSL-RT full-rate analog front end IC with integrated line driver. 857-865 - Andreas Wiesbauer, Martin Clara, Moritz Harteneck, Thomas Pötscher, Berthold Seger, Christoph Sandner, Christian Fleischhacker:
A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS. 866-873 - Karl Schrödinger, Jaro Stimma, Manfred Mauthe:
A fully integrated CMOS receiver front-end for optic Gigabit Ethernet. 874-880 - Shinji Yamashita, Satoshi Ide, Kazuyuki Mori, Atsushi Hayakawa, Norio Ueno, Kazuhiro Tanaka:
Novel cell-AGC technique for burst-mode CMOS preamplifier with wide dynamic range and high sensitivity for ATM-PON system. 881-886 - Simona Brigati, Paolo Colombara, Lucio D'Ascoli, Umberto Gatti, Tibor Kerekes, Piero Malcovati:
A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON. 887-894 - Bahram Zand, David A. Johns:
High-speed CMOS analog Viterbi detector for 4-PAM partial-response signaling. 895-903 - Andreas Demosthenous, John Taylor:
A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder. 904-910 - Olaf Schrey, Jürgen Huppertz, Goran Filimonovic, Arndt Bußmann, Werner Brockherde, Bedrich J. Hosticka:
A 1 K×1 K high dynamic range CMOS image sensor with on-chip programmable region-of-interest readout. 911-915 - Michael Oberle, Robert Reutemann, Jürgen Hertle, Qiuting Huang:
A 10-mW two-channel fully integrated system-on-chip for eddy-current position sensing [in biomedical devices]. 916-925 - Yuyun Liao, David B. Roberts:
A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature. 926-931 - Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka:
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. 932-940 - Tobias Gemmeke, Michael Gansen, Tobias G. Noll:
Implementation of scalable power and area efficient high-throughput Viterbi decoders. 941-948 - Wolfgang Horn, Heinz Zitta:
A robust smart power bandgap reference circuit for use in an automotive environment. 949-952 - Judith Maget, Marc Tiebout, Rainer Kraus:
Influence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25-μm CMOS technology. 953-958 - Nicola Da Dalt, Sven Derksen, Patrizia Greco, Christoph Sandner, Harald Schmid, Klaus Strohmayer:
A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology. 959-962
Volume 37, Number 8, August 2002
- Dandan Li, Yannis P. Tsividis:
Design techniques for automatically tuned integrated gigahertz-range active LC filters. 967-977 - Ugur Çilingiroglu, Luthuli Edem Dake:
Rank-order filter design with a sampled-analog multiple-winners-take-all core. 978-984 - Hee-Tae Ahn, David J. Allstot:
A 0.5-8.5 GHz fully differential CMOS distributed amplifier. 985-993 - Jung-Suk Goo, Hee-Tae Ahn, Donald J. Ladwig, Zhiping Yu, Thomas H. Lee, Robert W. Dutton:
A noise optimization technique for integrated low-noise amplifiers. 994-1002 - Salvatore Levantino, Carlo Samori, Andrea Bonfanti, Sander L. J. Gierkink, Andrea L. Lacaita, Vito Boccuzzi:
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. 1003-1011 - Toby Kwok-Kei Kan, Gerry C. T. Leung, Howard C. Luong:
A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer. 1012-1020 - Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu:
A wide-range delay-locked loop with a fixed latency of one clock cycle. 1021-1027 - Michael H. Perrott, Mitchell D. Trott, Charles G. Sodini:
A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis. 1028-1038 - Dorin Emil Calbaza, Yvon Savaria:
A direct digital period synthesis circuit. 1039-1045 - Ming-Dou Ker, Chien-Hui Chuang:
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers. 1046-1055 - Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen, Herman E. Maes:
An easy-to-use mismatch model for the MOS transistor. 1056-1064 - Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. 1065-1072 - Junichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio:
A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers. 1073-1079 - Falk Roewer, Ulrich Kleine:
A novel class of complementary folded-cascode opamps for low voltage. 1080-1083 - Chun Bing Guo, Chi-Wa Lo, Yu-Wing Choi, Issac Hsu, Toby Kwok-Kei Kan, David Leung, Alan N. L. Chan, Howard C. Luong:
A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection. 1084-1089 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz:
Addition to "An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers". 1090 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz:
Addition to "An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers". 1090
Volume 37, Number 9, September 2002
- Youn Sub Noh, Chul Soon Park:
PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit. 1096-1099 - Hisao Shigematsu, Masaru Sato, Tatsuya Hirose, Yuu Watanabe:
A 54-GHz distributed amplifier with 6-VPP output for a 40-Gb/s LiNbO3 modulator driver. 1100-1105 - Greg G. Freeman, Mounir Meghelli, Young Kwark, Steven Zier, Alexander V. Rylyakov, Michael Sorna, Todd Tanji, Oswin M. Schreiber, Keith Walter, Jae-Sung Rieh, Basanth Jagannathan, Alvin J. Joseph, Seshadri Subbanna:
40-Gb/s circuits built from a 120-GHz fT SiGe technology. 1106-1114 - Augusto Gutierrez-Aitken, Jim Matsui, Eric N. Kaneshiro, Bert K. Oyama, Donald Sawdai, Aaron K. Oki, Dwight C. Streit:
Ultrahigh-speed direct digital synthesizer using InP DHBT technology. 1115-1119 - George Georgiou, Yves Baeyens, Young-Kai Chen, Alan H. Gnauck, Carsten Gröpper, Peter Paschke, Rajasekhar Pullela, Mario Reinhold, Claus Dorschky, John Paul Mattia, Timo Winkler von Mohrenfels, Christoph Schulien:
Clock and data recovery IC for 40-Gb/s fiber-optic receiver. 1120-1125 - Tony K. Quach, Paul M. Watson, Wendy Okamura, Eric N. Kaneshiro, Augusto Gutierrez-Aitken, Thomas R. Block, Jack W. Eldredge, Thomas J. Jenkins, Lois T. Kehias, Aaron K. Oki, Donald Sawdai, Ryan J. Welch, Rick D. Worley:
Ultrahigh-efficiency power amplifier for space radar applications. 1126-1134 - Behzad Razavi:
Prospects of CMOS technology for high-speed optical communication circuits. 1135-1145 - Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki:
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. 1146-1151 - Yves Baeyens, George Georgiou, Joseph S. Weiner, Andreas Leven, Vincent Houtsma, Peter Paschke, Q. Lee, Rose F. Kopf, Yang Yang, L. Chua, C. Chen, C. T. Liu, Young-Kai Chen:
InP D-HBT ICs for 40-Gb/s and higher bitrate lightwave transceivers. 1152-1159 - Adiseno, Mohammed Ismail, Håkan K. Olsson:
A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers. 1162-1168 - Danielle Coffing, Eric Main, Mark Randol, Gina Szklarz:
A variable gain amplifier with 50-dB control range for 900-MHz applications. 1169-1175 - Mark P. van der Heijden, Henk C. de Graaff, Leo C. N. de Vreede:
A novel frequency-independent third-order intermodulation distortion cancellation technique for BJT amplifiers. 1176-1183 - Matthias Rickelt, Hans-Martin Rein:
A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits. 1184-1197 - David J. Walkey, Tom J. Smy, Ross G. Dickson, Jonathan S. Brodsky, David T. Zweidinger, Robert M. Fox:
Equivalent circuit modeling of static substrate thermal coupling using VCVS representation. 1198-1206 - Robert M. Fox, R. Chawla, William R. Eisenstadt, D. Hemmenway, J. Johnston:
Circuit for monitoring BJT RF performance using DC measurements. 1207-1210
Volume 37, Number 10, October 2002
- Vincent S. L. Cheung, Howard C. Luong, Wing-Hung Ki:
A 1-V 10.7-MHz switched-opamp bandpass ΣΔ modulator using double-sampling finite-gain-compensation technique. 1215-1225 - Jouko Vankka, Jaakko Pyykönen, Johan Sommarek, Mauri Honkanen, Kari A. I. Halonen:
A multicarrier GMSK modulator with on-chip D/A converter for base stations. 1226-1234 - Ahmed Nader Mohieldin, Ahmed A. Emira, Edgar Sánchez-Sinencio:
A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer. 1235-1243 - Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang, Yi-Chuan Liu, Chen-Yi Lee:
Design of a wide-band frequency synthesizer based on TDC and DVC techniques. 1244-1255 - Frank Ellinger, Werner Bächtold:
Novel principle for vector modulator-based phase shifters operating with only one control voltage. 1256-1259 - Hany F. Hammad, Alois P. Freundorfer, Yahia M. M. Antar:
Comprehensive study of multiband unconditional stabilization of common-source and common-gate MESFET transistors using feedback. 1260-1270 - Ganesh Kumar Balachandran, Phillip E. Allen:
Switched-current circuits in digital CMOS technology with low charge-injection errors. 1271-1281 - Fernando Antonio Pinto Barúqui, Antonio Petraglia, José E. Franca:
A 48-16-MHz CMOS SC decimation filter. 1282-1289 - Chris D. Holdenried, James W. Haslett, John G. McRory, R. Douglas Beards, A. J. Bergsma:
A DC-4-GHz true logarithmic amplifier: theory and implementation. 1290-1299 - Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi:
A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs. 1300-1306 - Perng-Fei Lin, James B. Kuo:
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. 1307-1317 - Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi:
High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. 1318-1325 - Jiandong Jiang, Edward K. F. Lee:
A low-power segmented nonlinear DAC-based direct digital frequency synthesizer. 1326-1330 - Mozhgan Mansuri, Dean Liu, Chih-Kong Ken Yang:
Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. 1331-1334 - Sungkyung Park, Gyudong Kim, Sin-Chong Park, Wonchan Kim:
A digital-to-analog converter based on differential-quad switching. 1335-1338 - Andrea Boni:
Op-amps and startup circuits for CMOS bandgap references with near 1-V supply. 1339-1343 - José Higino Correia, Ger de Graaf, Marian Bartek, Reinoud F. Wolffenbuttel:
A single-chip CMOS optical microspectrometer with light-to-frequency converter and bus interface. 1344-1347 - Po-Hui Yang, Jinn-Shyan Wang:
Low-voltage pulsewidth control loops for SOC applications. 1348-1351 - Ramchan Woo, Chi Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo:
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip. 1352-1355 - Sanghoon Hong, Sejun Kim, Jae-Kyung Wee, Seongsoo Lee:
Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier. 1356-1360
Volume 37, Number 11, November 2002
- Mozhgan Mansuri, Chih-Kong Ken Yang:
Jitter optimization based on phase-locked loop design parameters. 1375-1382 - Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. 1383-1395 - James W. Tschanz, James T. Kao, Siva G. Narendra, Raj Nair, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Vivek De:
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. 1396-1402 - Jacha Kim, Mark A. Horowitz:
Adaptive supply serial links with sub-1-V operation and per-pin clock recovery. 1403-1413 - Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang:
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator. 1414-1420 - Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar:
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. 1421-1432 - Eric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, Baker Mohammad:
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor. 1433-1440 - Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns:
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. 1441-1447 - Samuel D. Naffziger, Glenn Colón-Bonet, Timothy C. Fischer, Reid J. Riedlinger, Thomas J. Sullivan, Tom Grutkowski:
The implementation of the Itanium 2 microprocessor. 1448-1460 - Georgios K. Konstadinidis, Kevin Normoyle, Samson Wong, Sutikshan Bhutani, Harry Stuimer, Timothy Johnson, Alan P. Smith, Daniel Y. Cheung, Fabrizio Romano, Shifeng Yu, Sung-Hun Oh, Victor Melamed, Sridhar Narayanan, David Bunsey, Cong Khieu, Kevin J. Wu, Ralf Schmitt, Andy Dumlao, Massimo Sutera, Jade Chau, K. James Lin, William S. Coates:
Implementation of a third-generation 1.1-GHz 64-bit microprocessor. 1461-1469 - Mun-Kyu Choi, Byung-Gil Jeon, Nakwon Jang, Byung-Jun Min, Yoon-Jong Song, Sung-Yung Lee, Hyun-Ho Kim, Dong-Jin Jung, Heung-Jin Joo, Kinam Kim:
A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme. 1472-1478 - Toshiyuki Nishihara, Yasuyuki Ito:
A quasi-matrix ferroelectric memory for future silicon storage. 1479-1484 - Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi:
A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. 1485-1492 - Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che:
A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. 1493-1501 - June Lee, Heung-Soo Im, Dae-Seok Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyong-Hwa Lee, Sang Won Hwang, Sung-Soo Lee, Young-Ho Lim, Jae-Duk Lee, Jung-Dal Choi, Young-Il Seo, Jong-Sik Lee, Kang-Deog Suh:
High-performance 1-Gb-NAND flash memory with 0.12-μm technology. 1502-1509 - Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi:
Memory design using a one-transistor gain cell on SOI. 1510-1522 - Don Weiss, John J. Wuu, Victor Chin:
The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. 1523-1529 - Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal:
A 600-MHz VLIW DSP. 1532-1544 - James T. Kao, Masayuki Miyazaki, Anantha P. Chandrakasan:
A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture. 1545-1554 - Mark A. Bickerstaff, David Garrett, Tom Prokop, Charles Thomas, Benjamin Widdup, Gongyu Zhou, Linda M. Davis, Graeme Woodward, Chris Nicol, Ran-Hong Yan:
A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-μm CMOS. 1555-1564 - Leilei Song, Meng-Lin Yu, Michael S. Shaffer:
10- and 40-Gb/s forward error correction devices for optical communications. 1565-1573 - Takashi Hashimoto, Masahiro Ohashi, Masatoshi Matsuo, Shun-ichi Kuromaru, Toshihiro Mori-iwa, Mana Hamada, Yuji Sugisawa, Hiroto Tomita, Masashi Hoshino, Tsuyoshi Nakamura, Ken-ichi Ishida, Kazuhiro Watada, Taro Fukunaga, Junji Michiyama:
A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications. 1574-1581 - Geoff Jackson, Saleel V. Awsare, Ming-Bing Chang, Wen-Kuei Chen, Rodney Doan, Peter Holzmann, Dan Kahn, Chuan-Shin Rick Lin, Marian J. Macchi, Aditya Raina, Jesse (Bo-Hung) Wu, Brian (Bor-Wen) Yang:
A single-chip text-to-speech synthesis device utilizing analog nonvolatile multilevel flash storage. 1582-1589
Volume 37, Number 12, December 2002
- Peter C. S. Scholtens, Maarten Vertregt:
A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination. 1599-1609 - Jerry (Heng-Chih) Lin, Baher Haroun:
An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique. 1610-1617 - Shafiq M. Jamal, Daihong Fu, Nick C.-J. Chang, Paul J. Hurst, Stephen H. Lewis:
A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. 1618-1627 - Frank Henkel, Ulrich Langmann, André Hanke, Stefan Heinen, Elmar Wagner:
A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers. 1628-1635 - Richard Schreier, Jennifer Lloyd, Larry Singer, Donald Paterson, Mike Timko, Michael Hensley, Greg Patterson, Kevin Behel, James Zhou:
A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth. 1636-1644 - Robert H. M. van Veldhoven, Brian J. Minnis, Johannes A. (Hans) Hegt, Arthur H. M. van Roermund:
A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth. 1645-1652 - Sandeep K. Gupta, Victor Fong:
A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency. 1653-1661 - Jens Sauerbrey, Thomas Tille, Doris Schmitt-Landsiedel, Roland Thewes:
A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology. 1662-1669 - Paul T. M. van Zeijl, Jan-Wim Th. Eikenbroek, Peter Paul Vervoort, Suma Setty, Jurjen Tangenberg, Gary Shipton, Eric Kooistra, Ids C. Keekstra, Didier Belot, Klaas Visser, Erwin Bosma, Stephan C. Blaakmeer:
A 1.1-V 270-μA mixed-signal hearing aid chip. 1670-1678 - Paul T. M. van Zeijl, Jan-Wim Th. Eikenbroek, Peter Paul Vervoort, Suma Setty, Jurjen Tangenberg, Gary Shipton, Eric Kooistra, Ids C. Keekstra, Didier Belot, Klaas Visser, Erwin Bosma, Stephan C. Blaakmeer:
A Bluetooth radio in 0.18-μm CMOS. 1679-1687 - Masoud Zargari, David K. Su, C. Patrick Yue, Shahriar Rabii, David Weber, Brian J. Kaczynski, Srenik S. Mehta, Kalwant Singh, Sunetra Mendis, Bruce A. Wooley:
A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems. 1688-1694 - John F. Bulzacchelli, Hae-Seung Lee, James A. Misewich, Mark B. Ketchen:
Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate. 1695-1702 - Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe:
A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology. 1703-1709 - Rahul Magoon, Alyosha C. Molnar, Jeff Zachan, Geoff Hatcher, Woogeun Rhee:
A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer. 1710-1720 - Farbod Behbahani, Hamid Firouzkouhi, Ramesh Chokkalingam, Siamak Delshadpour, Alireza Kheirkhahi, Mohammad Nariman, Matteo Conta, Saket Bhatia:
A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection. 1721-1727 - Roberto Aparicio, Ali Hajimiri:
A noise-shifting differential Colpitts VCO. 1728-1736 - Pietro Andreani, Andrea Bonfanti, Luca Romanò, Carlo Samori:
Analysis and design of a 1.8-GHz CMOS LC quadrature VCO. 1737-1747 - Pierce Nagle, Phil Burton, Eugene Heaney, Finbarr McGrath:
A wide-band linear amplitude modulator for polar transmitters based on the concept of interleaving delta modulation. 1748-1756 - Curtis Ling, Raymond Montemayor, Alberto Cicalini, Kevin Wang, Lars C. Jansson, Lars Mucke, Pushp Trihka, Seendripu V. Kishore:
A low-power integrated tuner for cable telephony applications. 1757-1767 - Jun Cao, Michael M. Green, Afshin Momtaz, Kambiz Vakilian, David Chung, Keh-Chee Jen, Mario Caresosa, Xin Wang, Wee-Guan Tan, Yijun Cai, Ichiro Fujimori, Armond Hairapetian:
OC-192 transmitter and receiver in standard 0.18-μm CMOS. 1768-1780 - Jonathan E. Rogers, John R. Long:
A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS. 1781-1789 - Mounir Meghelli, Alexander V. Rylyakov, Lei Shan:
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems. 1790-1794 - Sheng Ye, Lars C. Jansson, Ian Galton:
A multiple-crystal interface PLL with VCO realignment to reduce phase noise. 1795-1803 - Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton:
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. 1804-1812 - Fuji Yang, Jay H. O'Neill, David Inglis, Joseph H. Othmer:
A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs. 1813-1821 - Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn:
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. 1822-1830 - John Pierdomenico, Scott Wurcer, Bob Day:
A 684-mW adaptive supply full-rate ADSL CO driver. 1831-1838 - KwangHo Yoon, Chanki Kim, Bumha Lee, Doyoung Lee:
Single-chip CMOS image sensor for mobile applications. 1839-1845 - David Stoppa, Andrea Simoni, Lorenzo Gonzo, Massimo Gottardi, Gian-Franco Dalla Betta:
Novel CMOS image sensor with a 132-dB dynamic range. 1846-1852 - Chen Xu, WeiQuan Zhang, Wing-Hung Ki, Mansun Chan:
A 1.0-V VDD CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25-μm CMOS process. 1853-1859 - John A. Geen, Steven J. Sherman, John F. Chang, Stephen R. Lewis:
Single-chip surface micromachined integrated gyroscope with 50°/h Allan deviation. 1860-1866 - Christoph Hagleitner, Dirk Lange, Andreas Hierlemann, Oliver Brand, Henry Baltes:
CMOS single-chip gas detection system comprising capacitive, calorimetric and mass-sensitive microsensors. 1867-1878 - Gary B. Levy, William Evans, John Ebner, Patrick Farrell, Mike Hufford, Bryan H. Allison, David Wheeler, Haiqing Lin, Olivier Prache, Eric Naviasky:
An 852×600 pixel OLED-on-silicon color microdisplay using CMOS subthreshold-voltage-scaling current drivers. 1879-1889
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