"A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 ..."

Sandeep K. Gupta, Victor Fong (2002)

> Home

Details and statistics

DOI: 10.1109/JSSC.2002.804358

access: closed

type: Journal Article

metadata version: 2023-09-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/GuptaF02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/GuptaF02
Sandeep K. Gupta, Victor Fong:
A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency. IEEE J. Solid State Circuits 37(12): 1653-1661 (2002)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.