"High-voltage transistor scaling circuit techniques for high-density ..."

Toru Tanzawa et al. (2002)

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DOI: 10.1109/JSSC.2002.803045

access: closed

type: Journal Article

metadata version: 2023-03-21

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Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi:
High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. IEEE J. Solid State Circuits 37(10): 1318-1325 (2002)

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