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"A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using ..."

Perng-Fei Lin, James B. Kuo (2002)

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DOI: 10.1109/JSSC.2002.803023

access: closed

type: Journal Article

metadata version: 2022-04-04

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Perng-Fei Lin, James B. Kuo:
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. IEEE J. Solid State Circuits 37(10): 1307-1317 (2002)

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