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Martin Clara
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2020 – today
- 2021
- [j5]Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Gerhard Knoblinger, Kamran Azadet:
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET. IEEE J. Solid State Circuits 56(12): 3655-3667 (2021) - [c13]Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet:
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET. ISSCC 2021: 174-176 - [c12]Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet:
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. ISSCC 2021: 176-178
2010 – 2019
- 2015
- [c11]Gil Engel, Martin Clara, Haiyang Zhu, Paul Wilkins:
A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz Fout. VLSIC 2015: 166- - 2012
- [c10]Daniel Gruber, Martin Clara, Berthold Seger:
A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOS. ESSCIRC 2012: 418-421 - 2011
- [j4]Martin Clara, Nicola Da Dalt:
Jitter Noise of Sampled Multitone Signals. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 652-656 (2011)
2000 – 2009
- 2008
- [c9]Martin Clara, Wolfgang Klatzer, Daniel Gruber, Arnold Marak, Berthold Seger, Wolfgang Pribyl:
A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS. ESSCIRC 2008: 262-265 - 2007
- [c8]Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori:
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS. ISSCC 2007: 250-600 - [i1]Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner:
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS. CoRR abs/0710.4838 (2007) - 2006
- [c7]Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl, Martin Clara, Luis Hernández, Daniel Gruber:
Clock jitter compensation for current steering DACs. ISCAS 2006 - 2005
- [j3]Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner:
A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS. IEEE J. Solid State Circuits 40(7): 1499-1505 (2005) - 2004
- [j2]Susana Patón, Antonio Di Giandomenico, Luis Hernández, Andreas Wiesbauer, Thomas Pötscher, Martin Clara:
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid State Circuits 39(7): 1056-1063 (2004) - [c6]Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos:
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. CICC 2004: 527-530 - [c5]Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner:
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS. DATE 2004: 223-226 - [c4]Dario Giotta, Peter Pessl, Martin Clara, Wolfgang Klatzer, Richard Gaggl:
Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOS. ESSCIRC 2004: 163-166 - [c3]Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner:
A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOS. ESSCIRC 2004: 339-342 - [c2]Martin Clara, Andreas Wiesbauer, Wolfgang Klatzer:
Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors. ISCAS (1) 2004: 285-288 - 2002
- [j1]Andreas Wiesbauer, Martin Clara, Moritz Harteneck, Thomas Pötscher, Berthold Seger, Christoph Sandner, Christian Fleischhacker:
A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS. IEEE J. Solid State Circuits 37(7): 866-873 (2002) - [c1]Martin Clara, Andreas Wiesbauer, Franz Kuttner:
A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS. CICC 2002: 437-440
Coauthor Index
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