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2020 – today
- 2021
[j14]Kasho Yamamoto
, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56(1): 165-178 (2021)- [j13]Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki:
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. Soft Comput. 25(3): 1731-1749 (2021) - [c26]Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka:
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. A-SSCC 2021: 1-3 - [c25]Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka:
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. ISSCC 2021: 64-66 - 2020
- [j12]Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. IEEE J. Solid State Circuits 55(1): 145-156 (2020) - [c24]Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka:
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. ASP-DAC 2020: 673-678 - [c23]Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC 2020: 138-140 - [i1]Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki:
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. CoRR abs/2004.03819 (2020)
2010 – 2019
- 2019
- [j11]Daisuke Oku, Kotaro Terada, Masato Hayashi, Masanao Yamaoka, Shu Tanaka, Nozomu Togawa:
A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. IEICE Trans. Inf. Syst. 102-D(9): 1696-1706 (2019) - [c22]Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto:
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. CICC 2019: 1-8 - [c21]Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE 2019: 1-6 - [c20]Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. ISSCC 2019: 52-54 - [c19]Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka:
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. VLSI Circuits 2019: 148- - 2018
- [c18]Takashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka:
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. ReConFig 2018: 1-8 - [c17]Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki:
Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. TPNC 2018: 111-123 - [c16]Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
An Ising model mapping to solve rectangle packing problem. VLSI-DAT 2018: 1-4 - 2017
- [j10]Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka:
Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing. Int. J. Netw. Comput. 7(2): 154-172 (2017) - [c15]Takuya Okuyama, Masato Hayashi, Masanao Yamaoka:
An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method. ICRC 2017: 1-6 - 2016
- [j9]Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. Int. J. Netw. Comput. 6(2): 195-211 (2016) - [j8]Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. IEEE J. Solid State Circuits 51(1): 303-309 (2016) - [c14]Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka:
FPGA-based Annealing Processor for Ising Model. CANDAR 2016: 436-442 - [c13]Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Masanao Yamaoka:
Computing architecture to perform approximated simulated annealing for Ising models. ICRC 2016: 1-8 - 2015
- [c12]Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. CANDAR 2015: 542-546 - [c11]Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. ISSCC 2015: 1-3 - [c10]N. Sugii, G. Jurczak, Masanao Yamaoka, A. Molnar, J. Tham, T. Piliszczuk, O. Nalamasu, J. Hausner, Shu Tanaka, Tadaaki Yamauchi, S. Sivaram, C. Diaz, W. Dai:
Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution? VLSIC 2015: 22- - 2014
- [c9]Masaki Hamamoto, Masanao Yamaoka:
An energy-efficient parallel-processing method based on master-hibernating DVFS. ISCAS 2014: 1724-1727 - 2013
- [c8]Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, Hiroyuki Mizuno:
Spatial computing architecture using randomness of memory cell stability under voltage control. ECCTD 2013: 1-4 - 2010
- [j7]Kiyoo Itoh, Masanao Yamaoka, Takashi Oshima:
Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. IEICE Trans. Electron. 93-C(3): 216-233 (2010)
2000 – 2009
- 2009
- [c7]Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC 2009: 701-704 - 2008
- [c6]Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara:
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC 2008: 286-289 - [c5]Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC 2008: 384-385 - 2007
- [c4]Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka:
Low-voltage limitations of memory-rich nano-scale CMOS LSIs. ESSCIRC 2007: 68-75 - [c3]Masanao Yamaoka, Takayuki Kawahara:
Operating-margin-improved SRAM with column-at-a-time body-bias control technique. ESSCIRC 2007: 396-399 - [c2]Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara:
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI 2007: 529-533 - 2006
- [j6]Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara:
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits 41(3): 705-711 (2006) - [j5]Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara:
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. IEEE J. Solid State Circuits 41(11): 2366-2372 (2006) - [c1]Masanao Yamaoka, Hidetoshi Onodera:
A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. SoCC 2006: 315-318 - 2005
- [j4]Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Motokazu Ozawa, Saneaki Tamaki, Mikio Furuyama, Tadashi Hoshi, Fumio Arakawa, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, Toshihiro Hattori:
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Trans. Electron. 88-C(4): 528-535 (2005) - [j3]Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada:
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J. Solid State Circuits 40(1): 186-194 (2005) - 2004
- [j2]Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi:
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits 39(6): 934-940 (2004) - 2002
- [j1]Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi:
A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. IEEE J. Solid State Circuits 37(5): 599-604 (2002)
Coauthor Index
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