13. VLSI Design 2000:
Calcutta,
India
13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India.
IEEE Computer Society 2000 
Tutorials
- Mahesh Mehendale, Sunil D. Sherlekar:
Power Reduction Techniques for Portable DSP Applications.
3
- Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar:
Theory and Applications of Cellular Automata for VLSI Design and Testing.
4
- Rubin A. Parekhji:
Test Techniques and Trade-offs for Embedded Cores and Systems.
5
- Laurence Nagel, Jaijeet S. Roychowdhury:
Computer-aided Design of RF Communication Systems: Techniques and Challenges.
6
- Ramesh Harjani:
Analog Circuits for Wireless Communications.
7
- Melvin A. Breuer, Sandeep K. Gupta:
New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits.
8
- Frank P. Higgins, Sudipta Bhawmik:
Core Based ASIC Design.
10
- Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake:
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.
11
- Kaushik Roy, Khurram Muhammad:
Low Power VLSI Signal Processing.
12
Keynote Address
- Avtar Saini:
Computing and Communication in the New Millennium.
15
Thursday Plenary Talks
Session 1A:
Low Power Design
- Liqiong Wei, Kaushik Roy, Vivek De:
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs.
24-29
- M. N. Mahesh, Mahesh Mehendale:
Low Power Realization of Residue Number System Based FIR Filters.
30-33
- Savithri Sundareswaran, R. Venkatesan, S. Bhaskar:
An Assertion Based Technique for Transistor Level Dynamic Power Estimation.
34-37
- Russell Henning, Chaitali Chakrabarti:
Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design.
38-43
- Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang:
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.
44-49
- Amit Sinha, Anantha Chandrakasan:
Energy Aware Software.
50-
Session 1B:
Formal Verification:
Session 1C:
Embedded Systems I
- Arvind Rajawat, M. Balakrishnan, Anshul Kumar:
nterface Synthesis: Issues and Approaches.
92
- T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik:
Processor Evaluation in an Embedded Systems Design Environment.
98-103
- Rainer Schaffer, Renate Merker, Francky Catthoor:
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
104-109
- Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan:
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.
110-113
- Robert P. Dick, Niraj K. Jha:
COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems.
114-
Session 2A:
Digital Imaging I
Session 2B:
Signal Integrity I
- Akis Doganis:
Interconnect Statistical Modeling: Structures and Measurement Methodologies.
150
- Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw:
Design and Analysis of Power Distribution Networks with Accurate RLC Models.
151-155
- Jinseong Choi, Sungjun Chun, Nanju Na, Madhavan Swaminathan, Larry D. Smith:
A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz Systems.
156-161
- Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari:
Inductive Noise Reduction at the Architectural Level.
162-167
- Shiyou Zhao, Kaushik Roy:
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits.
168-
Session 2C:
Testing I
- Manuel A. d'Abreu:
Manufacturing and Test Considerations in System-On-Chip Designs.
176-177
- Jitendra Khare, Hans T. Heineken, M. d'Abreu:
Cost Trade-Offs in System On Chip Designs.
178-184
- Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken:
Manufacturability and Testability Oriented Synthesis.
185-191
- Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, M. d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization.
192-197
- Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab:
Hierarchical Test Generation for Systems On a Chip.
198-
Session 3A:
High-level Synthesis
Session 3B:
Layout & Floorplanning
- Abdel Ejnioui, N. Ranganathan:
Routing on Switch Matrix Multi-FPGA Systems.
248-253
- Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna:
A Transistor Level Placement Tool for Custom Cell Generation.
254-257
- Abhijit Das:
On the Transistor Sizing Problem.
258-261
- Sushil Chandra Jain, Shashi Kumar, Anshul Kumar:
Evaluation of Various Routing Architectures for Multi-FPGA Boards.
262-267
- Yu-Liang Wu, Wangning Long, Hongbing Fan:
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks.
268-273
- Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Topological Routing Amidst Polygonal Obstacles.
274-279
- Helvio P. Peixoto, Margarida F. Jacome, Ander Royo:
A Tight Area Upper Bound for Slicing Floorplans.
280-
Session 3C:
Testing II
Banquet Address
Friday Plenary Talk
- Grant Martin:
Surviving the SOC Revolution: The Platform Approach to SOC Design.
325-
Session 4A:
Digital Imaging II
- Sabyasachi Dey, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya:
A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation.
330-335
- Rajesh T. N. Rajaram, Vinita Vasudevan:
Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD.
336-341
- Bedabrata Pain, Guang Yang, Monico Ortiz, Kenneth McCarty, Julie Heynssens, Bruce Hancock, Thomas Cunningham, Chris Wrigley, Charlie Ho:
A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability.
342-349
Session 4B:
Design
Session 4C:
Signal Integrity II
Session 5A:
Testing III
Session 5B:
Verification
- Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata:
Dataflow Analysis for Resource Contention and Register Leakage Properties.
418-423
- Subhash Chandra, Rajat Moona:
Retargetable Functional Simulator Using High Level Processor Models.
424-429
- Peter M. Maurer, William J. Schilp:
State-Machine Based Logic Simulation Using Three Logic Values.
430-435
- Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
Hierarchical Error Diagnosis Targeting RTL Circuits.
436-441
- Aarti Gupta, Pranav Ashar:
Fast Error Diagnosis for Combinational Verification.
442-448
- Yang Xia, Pranav Ashar:
Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture.
449-
Session 5C:
Embedded Systems II
Session 6A:
Analog / Mixed-signal Circuits
Session 6B:
Synthesis and Timing Analysis
Session 6C:
Testing IV
- Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta:
Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits.
544-549
- Sasikumar Cherubal, Abhijit Chatterjee:
An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards.
550-555
- Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee:
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.
556-561
- Kolin Paul, Dipanwita Roy Chowdhury:
Application of GF(2p) CA in Burst Error Correcting Codes.
562-567
- Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas:
Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell.
568-571
- Jeongjin Roh, Jacob A. Abraham:
A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters.
572-
VLSI Design 1999 Paper (late arrival)
Last update Tue Feb 14 04:12:38 2012
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