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ORCIDAbhijit Ghosh
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2020 – today
- 2024
[j14]Deepali Kulkarni, Abhijit Ghosh, Amey Girdhari, Shaomin Liu, L. Alexander Vance, Melissa Unruh, Joydeep Sarkar:
Enhancing pre-trained contextual embeddings with triplet loss as an effective fine-tuning method for extracting clinical features from electronic health record derived mental health clinical notes. Nat. Lang. Process. J. 6: 100045 (2024)- 2023
- [j13]Gilles Rainer
, Lewis Bridgeman, Abhijit Ghosh:
Neural Shading Fields for Efficient Facial Inverse Rendering. Comput. Graph. Forum 42(7) (2023) - 2022
- [j12]Abhijit Ghosh, Chittaranjan Mishra:
High-performance computation of pricing two-asset American options under the Merton jump-diffusion model on a GPU. Comput. Math. Appl. 105: 29-40 (2022) - 2021
- [j11]Abhijit Ghosh, Chittaranjan Mishra:
Highly efficient parallel algorithms for solving the Bates PIDE for pricing options on a GPU. Appl. Math. Comput. 409: 126411 (2021) - [j10]Abhijit Ghosh, Chittaranjan Mishra:
A Parallel Cyclic Reduction Algorithm for Pentadiagonal Systems with Application to a Convection-Dominated Heston PDE. SIAM J. Sci. Comput. 43(2): C177-C202 (2021)
2010 – 2019
- 2017
- [c23]Prasenjit Dey, Abhijit Ghosh, Tandra Pal:
Regularized Stacked Auto-Encoder Based Pre-training for Generalization of Multi-layer Perceptron. TPNC 2017: 232-242
2000 – 2009
- 2000
- [c22]Luc Séméria, Abhijit Ghosh:
Methodology for hardware/software co-verification in C/C++ (short paper). ASP-DAC 2000: 405-408 - [c21]Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh:
YAML: A Tool for Hardware Design Visualization and Capture. ISSS 2000: 9-17 - [c20]Abhijit Ghosh, Ranga Vemuri:
Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. VLSI Design 2000: 84-
1990 – 1999
- 1999
- [c19]Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao:
Hardware Synthesis from C/C++. DATE 1999: 387-389 - [c18]Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri:
Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. Great Lakes Symposium on VLSI 1999: 140-143 - [c17]Abhijit Ghosh, Ranga Vemuri:
Formal Verification of Synthesized Analog Designs. ICCD 1999: 40-45 - 1998
- [j9]José Monteiro, Srinivas Devadas, Abhijit Ghosh:
Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 279-284 (1998) - [j8]Fuchun Joseph Lin, Hong Liu, Abhijit Ghosh:
A Methodology for Feature Interaction Detection in the AIN 0.1 Framework. IEEE Trans. Software Eng. 24(10): 797-817 (1998) - 1997
- [j7]José Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White:
Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 121-127 (1997) - 1996
- [c16]Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer:
An observability-based code coverage metric for functional simulation. ICCAD 1996: 418-425 - 1995
- [j6]Amelia Shen, Srinivas Devadas, Abhijit Ghosh:
Probabilistic manipulation of Boolean functions using free Boolean diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 87-95 (1995) - [c15]José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh:
Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI 1995: 430-444 - 1994
- [j5]Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 426-436 (1994) - [c14]Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81 - 1993
- [j4]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Sequential test generation and synthesis for testability at the register-transfer and logic levels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 579-598 (1993) - [c13]José Monteiro, Srinivas Devadas, Abhijit Ghosh:
Retiming sequential circuits for low power. ICCAD 1993: 398-402 - [c12]Amelia Shen, Srinivas Devadas, Abhijit Ghosh:
Probabilistic construction and manipulation of free Boolean diagrams. ICCAD 1993: 544-583 - [c11]Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh:
Boolean factorization using multiple-valued minimization. ICCAD 1993: 606-611 - 1992
- [j3]Pranav Ashar, Abhijit Ghosh, Srinivas Devadas:
Boolean satisfiability and equivalence checking using general Binary Decision Diagrams. Integr. 13(1): 1-16 (1992) - [j2]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Heuristic minimization of Boolean relations using testing techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9): 1166-1172 (1992) - [c10]Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob K. White:
Estimation of Average Switching Activity in Combinational and Sequential Circuits. DAC 1992: 253-259 - [c9]Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer:
On average power dissipation and random pattern testability of CMOS combinational logic networks. ICCAD 1992: 402-407 - 1991
- [j1]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Test generation and verification for highly sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 652-667 (1991) - [c8]Pranav Ashar, Abhijit Ghosh, Srinivas Devadas:
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD 1991: 259-264 - [c7]Srinivas Devadas, Kurt Keutzer, Abhijit Ghosh:
Recent progress in synthesis for testability. VTS 1991: 22-29 - 1990
- [c6]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Verification of Interacting Sequential Circuits. DAC 1990: 213-219 - [c5]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Sequential Test Generation at the Register-Transfer and Logic Levels. DAC 1990: 580-586 - [c4]Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD 1990: 84-87 - [c3]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Heuristic minimization of Boolean relations using testing techniques. ICCD 1990: 277-281 - [c2]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Sequential logic synthesis for testability using register-transfer level descriptions. ITC 1990: 274-283
1980 – 1989
- 1989
- [c1]Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Test generation for highly sequential circuits. ICCAD 1989: 362-365
Coauthor Index
aka: Srinivas Devadas
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