ITC 2006:
Santa Clara, California, USAScott Davidson , Anne Gattiker (Eds.):
2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006.
IEEE 2006, ISBN 1-4244-0292-1
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Lee Whetsel :
A High Speed Reduced Pin Count JTAG Interface.
1-10
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Jeff Rearick ,
Aaron Volz :
A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing.
1-8
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Hung-chi Lihn :
Reusable, Low-cost, and Flexible Multidrop System JTAG Architecture.
1-10
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conf/itc/TendolkarBSPGKCBTTA06 Nandu Tendolkar ,
Dawit Belete ,
Bill Schwarz ,
Bob Podnar ,
Akshay Gupta ,
Steve Karako ,
Wu-Tung Cheng ,
Alex Babin ,
Kun-Han Tsai ,
Nagesh Tamarapalli ,
Greg Aldrich :
Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.
1-9
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conf/itc/StellariSDWVWPR06 export record as
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Fang Xu :
Perfect data reconstruction algorithm of time interleaved ADCs.
1-6
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Toai Vo ,
Zhiyuan Wang ,
Ted Eaton ,
Pradipta Ghosh ,
Huai Li ,
Young Lee ,
Weili Wang ,
Hong Shin Jun ,
Rong Fang ,
Dan Singletary ,
Xinli Gu :
Design for Board and System Level Structural Test and Diagnosis.
1-10
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Teresa L. McLaurin :
The Challenge of Testing the ARM CORTEX-A8/sup TM/ Microprocessor Core.
1-10
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conf/itc/KalyanaramanKVC06 export record as
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David E. Lackey :
Efficient Latch and Clock Structures for System-on-Chip Test Flexibility.
1-7
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Xiaoding Chen ,
Michael S. Hsiao :
Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation.
1-10
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conf/itc/BayraktarogluHW06 export record as
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Chong Zhao ,
Sujit Dey :
Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits.
1-10
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conf/itc/AlmukhaizimMYV06 export record as
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conf/itc/KajiharaMTWMHS06 export record as
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Leonard Lee ,
Li-C. Wang :
An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space.
1-10
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conf/itc/IyengarYYABDFGJMTW06 Vikram Iyengar ,
Toshihiko Yokota ,
Kazuhiro Yamada ,
Theo Anemikos ,
Bob Bassett ,
Mike Degregorio ,
Rudy Farmer ,
Gary Grise ,
Mark Johnson ,
Dave Milton ,
Mark Taylor ,
Frank Woytowich :
At-Speed Structural Test For High-Performance ASICs.
1-10
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Jeffrey L. Roehr :
Very-Low Voltage (VLV) and VLV Ratio (VLVR) Testing for Quality, Reliability, and Outlier Detection.
1-6
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Doug Heaberlin :
The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution.
1-10
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conf/itc/RemersaroLZRPR06 export record as
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conf/itc/VijayaraghavanSSS06 export record as
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Martin Dresler :
Technique to Detect RF Interface and Contact Issues During Production Testing.
1-6
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Frank Demmerle :
Integrated RF-CMOS Transceivers challenge RF Test.
1-8
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Heiko Ehrenberg :
IEEE P1581 - Getting More Board Test Out of Boundary Scan.
1-10
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Rosa D. Reinosa :
Lead Free Through Hole Technology (THT) and Contact Repeatability in In-Circuit Test.
1-10
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Jochen Rivoir :
Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration.
1-10
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Peter Maxwell :
The Design, Implementation and Analysis of Test Experiments.
1-9
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Eric Johnson :
Structural Testing of High-Speed Serial Buses: A Case Study Analysis.
1-9
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Chris Allsup :
The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time.
1-9
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