ISCAS 2011:
Rio de Janeiro, BrazilAnalog to Digital Converters I
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conf/iscas/MacphersonTH11 export record as
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conf/iscas/KamalinejadML11
Amplifiers
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Low-Dropout Regulator
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S. S. Chong ,
P. K. Chan :
A quiescent power-aware low-voltage output capacitorless low dropout regulator for SoC applications.
37-40
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Chenchang Zhan ,
Wing-Hung Ki :
An output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction for SoC.
45-48
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Edward N. Y. Ho ,
Philip K. T. Mok :
Design optimization of an output capacitor-less low dropout regulator with compensation capcitance reduction and slew-rate enhancement technique.
53-56
Memory Circuits I
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Life Science Systems & Applications
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Image & Video Coding
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Adaptive Techniques in Signal and Image Processing Applications
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FIR Digital Filters
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Mohammad Ahsan ,
Tapio Saramaki :
"A MATLAB based optimum multiband FIR filters design program following the original idea of the Remez multiple exchange algorithm".
137-140
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Ya Jun Yu :
Design of variable bandedge FIR filters with extremely large bandedge variation range.
141-144
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Wen Bin Ye ,
Ya Jun Yu :
Switching activity analysis and power estimation for multiple constant multiplier block of FIR filters.
145-148
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Digitally Intensive Frequency Synthesis Architectures for the Nano-Scale - Part I
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conf/iscas/BrandonisioK11 export record as
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conf/iscas/KlumperinkDRNG11 export record as
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conf/iscas/Gonzalez-DiazPM11
Wireline Communications I
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Advanced Transmitter Design Techniques
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Oscillators
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Li Lu ,
Changzhi Li ,
Jenshan Lin :
A regulated 3.1-10.6 GHz linear dual-tuning differential ring oscillator for UWB applications.
225-228
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Power Converter I
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conf/iscas/Murthy-BellurK11 export record as
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Yi Zhang ,
Dongsheng Ma :
Integrated SIMO DC-DC converter with on-line charge meter for adaptive PCCM operation.
245-248
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Moises Tanca V. ,
Ivo Barbi :
Nonisolated high step-up stacked dc-dc converter based on boost converter elements for high power application.
249-252
Analog to Digital Converters II
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Ji-Eun Jang :
Comparator-based switched-capacitor pipelined ADC with background offset calibration.
253-256
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Low-Noise Amplifiers
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conf/iscas/Becerra-AlvarezRS11 export record as
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Emerging Energy & Power Integrated Circuits
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Xiaocheng Jing ,
Philip K. T. Mok :
Ultra-fast hysteretic single-inductor-dual-output boost regulator with predictable noise spectrum and minimized cross-regulation.
297-300
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Memory Circuits II
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conf/iscas/PapandreouPPSBLE11
Experiences with CAS teaching
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conf/iscas/OtoakhiaJAAMSK11 export record as
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conf/iscas/Albo-CanalsP11 export record as
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Visual Signal Analysis & Understanding
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Detection and Estimation
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B. Liao ,
S. C. Chan :
DOA estimation of coherent signals for uniform linear arrays with mutual coupling.
377-380
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Diego Bellan :
An improved model of jitter effects in analog-to-digital conversion.
381-384
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Digital Filter Design & Implementation
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Yu Pan ,
Pramod Kumar Meher :
Efficient coefficient partitioning for decomposed DA-based inner-product computation.
406-409
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conf/iscas/BruckmannFHKKT11
Digitally Intensive Frequency Synthesis Architectures for the Nano-Scale - Part II
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Ulrich L. Rohde ,
Ajay K. Poddar :
Digital frequency synthesizer using adaptive mode-coupled resonator mechanism for low phase noise and low jitter applications.
414-417
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Paul-Peter Sotiriadis :
Spurs suppression and deterministic jitter correction in all-digital frequency synthesizers, current state and future directions.
422-425
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Wireline Communications II
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Won-Young Lee ,
Lee-Sup Kim :
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation.
430-433
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conf/iscas/Zargaran-YazdMS11
Advanced Baseband Design Techniques
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conf/iscas/DSouzaCPAZSB11 export record as
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conf/iscas/Cruz-RoldanBG11 export record as
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PLL
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conf/iscas/PeslouanMTDBB11 export record as
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Power Converter II
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Franz Lukasch :
Cost efficient mains powered supply concepts for wireless sensor nodes.
502-505
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Analog to Digital Converters III
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Shanthi Pavan :
The inconvenient truth about alias rejection in continuous time ΔΣ converters.
526-529
Wireless Circuits
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conf/iscas/ReinischGUWHPH11 export record as
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Design Techniques for Storage Elements
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Keisuke Inoue ,
Mineo Kaneko :
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis.
550-553
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conf/iscas/SelimisKAHGLSHT11
VLSI for Video Systems I
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conf/iscas/DinizZTSBSPA11 export record as
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conf/iscas/LivramentoMMG11
Pedagogical Innovations in Circuits, Signals & Systems Education
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Tokunbo Ogunfunmi :
Analysis of assessment using signals, systems concept inventory for systems courses.
595-598
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Babak Ayazifar :
Rethinking Fourier's legacy in signals and systems education.
599-602
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Visual Signal Coding & Communications
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Blind Signal Processing
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conf/iscas/BatalheiroPH11 export record as
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IC Implementation of DSP Algorithms
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Spike-Based Systems
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Yingxue Wang ,
Shih-Chii Liu :
Mismatch reduction through dendritic nonlinearities in a 2D silicon dendritic neuron array.
677-680
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MIMO Communications Systems
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Cryptography & Security for Communications Systems
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Synchronization
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Jin Fan :
Synchronization of the Kuramoto model with multi-scale-free property.
729-732
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conf/iscas/MagistrisBTM11 export record as
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Power Converter III
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conf/iscas/Nagashima1WSK11 export record as
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conf/iscas/YangHHLWFDCC11 export record as
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conf/iscas/HuangSLCSCDC11 export record as
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conf/iscas/Ribes-MalladaLG11
Tools & Methods for Analog Circuit Design
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conf/iscas/GiustolisiMP11 export record as
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Circuits for Biomedical Systems & Bio-Inspired Systems
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conf/iscas/Al-RawhaniCCC11 export record as
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Power Eletronic Circuits I
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Loai G. Salem ,
Rinkle Jain :
A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters.
825-828
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conf/iscas/Mendez-DelgadoS11
Low-Power Circuits II
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Jun Xu ,
Xiangku Li :
Improve accuracy of delay element by filtering false path for low power desychronized circuits.
845-848
Image Processing & Analysis
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conf/iscas/Rummele-WernerPBHB11 export record as
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Neuromorphic Circuits & Systems
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Low Voltage, Low Power Circuits
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conf/iscas/Molinar-SolisGMR11 export record as
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Wireless, Wearable & Implantable/Injectable Technology II
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conf/iscas/MirbozorgiNM11 export record as
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Power Eletronic Circuits II
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VLSI for Video Systems II
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Milad Ghantous ,
Magdy Bayoumi :
P2 E-DWT: A parallel and pipelined efficient VLSI architecture of 2-D Discrete Wavelet Transform.
941-944
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Juan Du ,
Lu Yu :
A parallel and area-efficient architecture for deblocking filter and Adaptive Loop Filter.
945-948
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DSP for Communications
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conf/iscas/MadanayakeBB11 export record as
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Gabriel N. Maggio ,
Mario R. Hueda :
Design and parallel implementation of an adaptive baseline wander compensator for high-speed optical coherent receivers.
969-972
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Neil Jacklin ,
Zhi Ding :
A convex optimization approach to reducing peak-to-average-power ratio in OFDM.
973-976
ADC and PLL
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Broadband Analog Signal Processing Circuits
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Zhenqi Chen ,
Fa Foster Dai :
A 3mW 8-Bit radiation-hardened-by-design DAC for ultra-wide temperature range from -180°C to 120°C.
997-1000
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Life Science Applications
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conf/iscas/GoldsteinKRXVC11 export record as
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Chun-Yen Wang ,
Kea-Tiong Tang :
Active noise cancellation of motion artifacts in pulse oximetry using isobestic wavelength light source.
1029-1032
Power System
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conf/iscas/Andrade-RomeroAR11 export record as
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Testing & Arithmetic Circuits
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conf/iscas/PapadopoulosTM11 export record as
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Digital Signal Processing Applications
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Thiago Ciodaro :
Optimal signal discrimination in a Low signal-to-noise ratio environment.
1085-1088
Neural Networks II
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Qingshan Liu ,
Jun Wang :
A one-layer recurrent neural network for constrained single-ratio linear fractional programming.
1089-1092
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Ari Paasio :
Prototype rotation based assisted image analysis for 3D vision system.
1101-1104
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Sigma Delta ADC
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conf/iscas/FakhouryJKNL11 export record as
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Julian Garcia ,
Ana Rusu :
High-order continuous-time incremental ΣΔ ADC for multi-channel applications.
1121-1124
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Oscillators & Frequency Synthesizers
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conf/iscas/CasaleiroLOFS11 export record as
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conf/iscas/Sanchez-AzquetaCA11 export record as
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Confession Session:
Learning from Others Mistakes
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conf/iscas/AbshireBBCCCCCDDDDEEILLTTZ11 Pamela Abshire ,
Amine Bermak ,
Raphael Berner ,
Gert Cauwenberghs ,
Shoushun Chen ,
Jennifer Blain Christen ,
Timothy G. Constandinou ,
Eugenio Culurciello ,
Marc Dandin ,
Timir Datta ,
Tobi Delbrück ,
Piotr Dudek ,
Amir Eftekhar ,
Ralph Etienne-Cummings ,
Giacomo Indiveri ,
Matthew K. Law ,
Bernabé Linares-Barranco ,
Jonathan Tapson ,
Wei Tang ,
Yiming Zhai :
Confession session: Learning from others mistakes.
1149-1162
Arithmetic Circuits I
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conf/iscas/MuralidharanC11 export record as
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conf/iscas/SchinianakisS11 export record as
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Design, Project & Learning Technology Innovations in Circuits, Signals & Systems Education
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Yong Lian :
An online adaptive tutoring system for design-centric courses.
1191-1194
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conf/iscas/DehaeneGDDMNHW11 export record as
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Physical Design & Clock Synthesis
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Jason Cong ,
John Lee ,
Guojie Luo :
A unified optimization framework for simultaneous gate sizing and placement under density constraints.
1207-1210
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Multimedia Compression & Quality
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Zhenzhong Chen ,
Yap-Peng Tan :
Frame-level quantization control for perceptual quality constrained H.264/AVC video coding.
1231-1234
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DSP Implementation
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conf/iscas/MadanayakeCODB11 export record as
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Recent Advances in Linear & Non-Linear Adaptive Filters
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conf/iscas/RadhakrishnanJ11 export record as
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UWB Circuits & Systems I
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Low-Density Parity-Check Decoder Design
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Xinmiao Zhang ,
Fang Cai :
Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding.
1303-1306
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Bifurcation and Chaos
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conf/iscas/CallegariPSS11 export record as
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Zbigniew Galias :
On rigorous integration of piece-wise linear continuous systems.
1339-1342
Integrated Power Converters & Energy Harvesting
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conf/iscas/FlorentinoFSFG11 export record as
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Delta-Sigma Modulator
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conf/iscas/FitzgibbonKM11 export record as
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conf/iscas/Pena-PerezBM11 export record as
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Analog Filtering & Signal Processing
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Noise Immunity & ESD
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Emre Salman :
Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits.
1411-1414
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Arithmetic Circuits II
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Jun Xu ,
Hong Wang :
Desynchronize a legacy floating-point adder with operand-dependant delay elements.
1427-1430
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conf/iscas/JohanssonGDW11
Circuits for Biomedical Systems I
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