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ORCIDRinkle Jain
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2020 – today
- 2024
[c9]Rinkle Jain, Shunjiang Xu, Rajiv Kaushal, Carlos Mariscal, Humberto Caballero, Tamir Salus, Christopher Schaef, Anup Deka, Aruna Payala, Keng Chen, Huong Do, Jonathan Douglas:
28.6 An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling Vertical Power Delivery in Multi-kW Systems-on-Package. ISSCC 2024: 466-468- 2023
- [j8]Minxiang Gong
, Hua Chen, Xin Zhang, Rinkle Jain, Arijit Raychowdhury:
A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer. IEEE J. Solid State Circuits 58(4): 1002-1014 (2023) - [j7]Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Timothy F. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, Brent R. Carlton:
A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks. IEEE J. Solid State Circuits 58(5): 1285-1298 (2023) - 2021
- [c8]Hao Luo, Somnath Kundu, Chun C. Lee, Rinkle Jain, Sarah Shahraini, Eduardo Alban, Timo Huusari, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton:
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS. CICC 2021: 1-2
2010 – 2019
- 2019
- [j6]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2018
- [j5]Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, Rinkle Jain, Sheldon Weng, Stephen T. Kim, George E. Matthew, Nachiket V. Desai, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. IEEE J. Solid State Circuits 53(1): 8-19 (2018) - [c7]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - 2017
- [c6]Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De:
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. ISSCC 2017: 336-337 - 2016
- [j4]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 18-30 (2016) - 2015
- [j3]Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(8): 1809-1819 (2015) - [c5]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC 2015: 1-3 - 2014
- [j2]Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep Kulkarni, James W. Tschanz, Vivek De:
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 49(4): 917-927 (2014) - [c4]Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, James W. Tschanz, Krishnan Ravichandran, Vivek De:
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS. CICC 2014: 1-4 - [c3]Sally Safwat, Rinkle Jain, Dawson Kesling:
A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters. ISCAS 2014: 1664-1667 - [c2]Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - 2011
- [c1]Loai G. Salem, Rinkle Jain:
A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters. ISCAS 2011: 825-828
2000 – 2009
- 2006
- [j1]Rinkle Jain, Ned Mohan, Rajapandian Ayyanar, Robbert M. Button:
A Comprehensive Analysis of Hybrid Phase-Modulated Converter With Current-Doubler Rectifier and Comparison With Its Center-Tapped Counterpart. IEEE Trans. Ind. Electron. 53(6): 1870-1880 (2006)
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