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ORCIDAlexandre Solon Nery
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2020 – today
- 2021
[j11]Carlos Antônio Campos Jorge
, Alexandre Solon Nery, Alba C. M. A. Melo, Alfredo Goldman:
A CPU-FPGA heterogeneous approach for biological sequence comparison using high-level synthesis. Concurr. Comput. Pract. Exp. 33(4) (2021)- [j10]Adrianno Sampaio, Alexandre da Costa Sena, Alexandre Solon Nery:
Enabling heterogeneous ray-tracing acceleration in edge/cloud architectures. Concurr. Comput. Pract. Exp. 33(11) (2021) - [j9]Brunno F. Goldstein, Vinay C. Patil, Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe M. G. França, Sandip Kundu:
Preventing DNN Model IP Theft via Hardware Obfuscation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 267-277 (2021) - [c18]Brunno F. Goldstein, Victor da Cruz Ferreira, Sudarshan Srinivasan, Dipankar Das, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França:
A Lightweight Error-Resiliency Mechanism for Deep Neural Networks. ISQED 2021: 311-316 - 2020
- [c17]Brunno F. Goldstein, Sudarshan Srinivasan, Dipankar Das, Kunal Banerjee, Leandro Santiago de Araújo, Victor da Cruz Ferreira, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França:
Reliability Evaluation of Compressed Deep Learning Models. LASCAS 2020: 1-5
2010 – 2019
- 2019
- [j8]Leandro A. J. Marzulo, Alexandre da Costa Sena, Alexandre Solon Nery, Cristiana Bentes, Igor Machado Coelho, Maria Clicia Stelling de Castro, Saulo T. Oliveira, Tiago A. O. Alves, Felipe M. G. França:
DTM@GPU: Characterizing and evaluating trace redundancy in GPU. Concurr. Comput. Pract. Exp. 31(18) (2019) - [j7]Leandro Rouberte, Alexandre da Costa Sena, Alexandre Solon Nery, Leandro A. J. Marzulo, Tiago A. O. Alves, Felipe M. G. França:
DF-DTM: Dynamic Task Memoization and reuse in dataflow. Concurr. Comput. Pract. Exp. 31(18) (2019) - [j6]Alexandre Solon Nery, Alexandre da Costa Sena, Leandro Soares Guedes:
An efficient pathfinding system in FPGA for edge/fog computing. Int. J. Grid Util. Comput. 10(3): 212-223 (2019) - [j5]Marcos Paulo Rocha, Felipe M. G. França, Alexandre Solon Nery, Leandro Soares Guedes:
An optimised dataflow engine for GPGPU stream processing. Int. J. Grid Util. Comput. 10(3): 248-257 (2019) - [c16]Leandro Santiago de Araújo, Victor da Cruz Ferreira, Brunno Figueiroa Goldstein, Alexandre Solon Nery, Leandro Augusto Justen Marzulo, Sandip Kundu, Felipe Maia Galvão França:
Hardware-Accelerated Similarity Search with Multi-Index Hashing. DASC/PiCom/DataCom/CyberSciTech 2019: 733-740 - [c15]Adrianno Sampaio, Alexandre da Costa Sena, Alexandre Solon Nery:
A Re-Configurable Ray-Triangle Vector Accelerator for Emerging Fog Architectures. IPDPS Workshops 2019: 826-833 - [c14]Victor da Cruz Ferreira, Alexandre Solon Nery, Leandro A. J. Marzulo, Leandro Santiago, Diego Fonseca Pereira de Souza, Brunno F. Goldstein, Felipe M. G. França, Vladimir Castro Alves:
A Feasible FPGA Weightless Neural Accelerator. ISCAS 2019: 1-5 - 2018
- [c13]Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe Maia Galvão França:
A Smart Disk for In-Situ Face Recognition. IPDPS Workshops 2018: 1241-1249 - [c12]Alexandre Solon Nery, Alexandre da Costa Sena:
Efficient A* Co-processor for Reconfigurable Gaming Devices. SBGames 2018: 97-106 - 2017
- [c11]Alexandre Solon Nery, Alexandre da Costa Sena, Leandro Soares Guedes:
Efficient Pathfinding Co-Processors for FPGAs. SBAC-PAD (Workshops) 2017: 97-102 - [c10]Marcos Paulo Rocha, Felipe M. G. França, Alexandre Solon Nery, Leandro Soares Guedes:
Dataflow Programming for Stream Processing. SBAC-PAD (Workshops) 2017: 103-108 - 2014
- [c9]Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal:
A framework for automatic custom instruction identification on multi-issue ASIPs. INDIN 2014: 428-433 - [c8]Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal:
Automatic complex instruction identification for efficient application mapping onto ASIPs. LASCAS 2014: 1-4 - 2013
- [j4]Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França:
Efficient hardware implementation of Ray Tracing based on an embedded software for intersection computation. J. Syst. Archit. 59(3): 176-185 (2013) - [j3]Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França:
Hardware reuse in modern application-specific processors and accelerators. Microprocess. Microsystems 37(6-7): 684-692 (2013) - [j2]Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak:
Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. Microprocess. Microsystems 37(6-7): 739-749 (2013) - [c7]Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak, Henk Corporaal:
A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension. ICA3PP (1) 2013: 346-356 - 2012
- [c6]Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak:
Interactive Volume Rendering Based on Ray-Casting for Multi-core Architectures. VECPAR 2012: 177-186 - 2011
- [c5]Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França:
Hardware Reuse in Modern Application-Specific Processors and Accelerators. DSD 2011: 140-147 - [c4]Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak:
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. DSD 2011: 511-518 - [c3]Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak:
Massively Parallel Identification of Intersection Points for GPGPU Ray Tracing. ICA3PP (2) 2011: 14-23 - [c2]Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak:
A parallel architecture for ray-tracing with an embedded intersection algorithm. ISCAS 2011: 1491-1494
2000 – 2009
- 2009
- [j1]Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França:
A massively parallel hardware architecture for ray-tracing. Int. J. High Perform. Syst. Archit. 2(1): 26-34 (2009) - [c1]Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França:
GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids. DSD 2009: 211-216
Coauthor Index
aka: Felipe Maia Galvão França
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