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ORCIDReConFig 2016: Cancun, Mexico
- Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass:
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016. IEEE 2016, ISBN 978-1-5090-3707-0 - Graham Schelle:
Keynote 1 - Growing the ReConFig community through python, zynq and hardware overlays. 1 - Skip Booth:
Keynote 2 - FPGAs in the datacenter - A software view. 1 - Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia:
Technical demonstration session: Software toolflow for FPGA bitstream obfuscation. 1-2 - Gundolf Kiefer, Matthias Vahl, Julian Sarcher, Michael Schaeferling:
A configurable architecture for the generalized hough transform applied to the analysis of huge aerial images and to traffic sign detection. 1-7 - Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo
, Luca Benini:
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. 1-8 - Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen:
A multi-functional memory unit with PLA-based reconfigurable decoder. 1-7 - Matej Bartik, Sven Ubik, Pavel Kubalík:
A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time. 1-6 - Jaco A. Hofmann, Jens Korinth, Andreas Koch:
A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications. 1-8 - Farnoud Farahmand, Ekawat Homsirikamol, Kris Gaj:
A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests. 1-7 - Robért Glein, Florian Rittner, Albert Heuberger:
Adaptive single-event effect mitigation for dependable processing systems. 1-8 - Ali Asgar Sohanghpurwala, Peter M. Athanas:
An effective probability distribution SAT solver on reconfigurable hardware. 1-6 - João Canas Ferreira, Jose Fonseca:
An FPGA implementation of a long short-term memory neural network. 1-8 - Paul Rogers, Rajesh Kavasseri, Scott C. Smith:
An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors. 1-6 - Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. 1-6 - Michail S. Vavouras, Christos-Savvas Bouganis:
Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs. 1-6 - N. Nila-Olmedo, Fortino Mendoza-Mondragón, Alejandro Espinosa-Calderon, Moreno:
ARM+FPGA platform to manage solid-state-smart transformer in smart grid application. 1-6 - Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil:
Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. 1-6 - Pham Nam Khanh, Khin Mi Mi Aung, Akash Kumar:
Automatic framework to generate reconfigurable accelerators for option pricing applications. 1-8 - Thaddeus Koehn, Peter Athanas:
Automating structured matrix-matrix multiplication for stream processing. 1-6 - Sen Ma, David Andrews, Shanyuan Gao, Jaime Cummins:
Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud. 1-6 - Tiziana Fanni, Luigi Raffo:
Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems. 1-4 - Tobias Lieske, Marc Reichenbach, Burkhard Ringlein, Dietmar Fey:
Dataflow optimization for programmable embedded image preprocessing accelerators. 1-8 - Siavash Rezaei, César-Alejandro Hernández-Calderón, Saeed Mirzamohammadi, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alex Nicolau, Michael J. Prather:
Data-rate-aware FPGA-based acceleration framework for streaming applications. 1-6 - Atil U. Ay, Erdinç Öztürk, Francisco Rodríguez-Henríquez, Erkay Savas:
Design and implementation of a constant-time FPGA accelerator for fast elliptic curve cryptography. 1-8 - Akihiko Hamada, Hiroki Matsutani:
Design and implementation of hardware cache mechanism and NIC for column-oriented databases. 1-6 - Florian Rittner, Robért Glein, Albert Heuberger:
Detection and Isolation of permanent faults in FPGAs with remote access. 1-4 - Andres Jacoby, Daniel Llamocca:
Dual fixed-point CORDIC processor: Architecture and FPGA implementation. 1-8 - Thorbjörn Posewsky, Daniel Ziener:
Efficient deep neural network acceleration through FPGA-based batch processing. 1-8 - Tobias Kalb, Diana Göhringer:
Enabling dynamic and partial reconfiguration in Xilinx SDSoC. 1-7 - Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. 1-6 - Habib ul Hasan Khan, Diana Göhringer:
FPGA debugging by a device start and stop approach. 1-6 - Kledermon Garcia, Duarte Lopes de Oliveira, Roberto d'Amore, Lester de Abreu Faria, Joao Luis V. Oliveira:
FPGA implementation of optimized XBM specifications by transformation for AFSMs. 1-6 - Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara:
FPGA-based encrypted network traffic identification at 100 Gbit/s. 1-6 - Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck:
Hardware-accelerated pose estimation for embedded systems using Vivado HLS. 1-7 - Rasha Karakchi, Jordan A. Bradshaw, Jason D. Bakos:
High-level synthesis of a genomic database search engine. 1-6 - Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So:
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. 1-6 - Bernhard Jungk, Marc Stöttinger:
Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations. 1-7 - Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann:
Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. 1-7 - Lukas Johannes Jung, Christian Hochberger:
Optimal processor interface for CGRA-based accelerators implemented on FPGAs. 1-7 - Khaled E. Ahmed, Mohamed R. M. Rizk, Mohammed M. Farag:
Overloaded CDMA interconnect for Network-on-Chip (OCNoC). 1-7 - Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings:
Packing a modern Xilinx FPGA using RapidSmith. 1-6 - Ernst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars:
Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms. 1-8 - Paolo Di Febbo, Stefano Mattoccia, Carlo Dal Mutto:
Real-time image distortion correction: Analysis and evaluation of FPGA-compatible algorithms. 1-6 - Qianqiao Chen, Vaibhawa Mishra, Georgios Zervas:
Reconfigurable computing for network function virtualization: A protocol independent switch. 1-6 - Vaibhawa Mishra, Qianqiao Chen, Georgios Zervas:
REoN: A protocol for reliable software-defined FPGA partial reconfiguration over network. 1-7 - Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich:
ReOrder: Runtime datapath generation for high-throughput multi-stream processing. 1-8 - Jens Rettkowski, Konstantin Friesen, Diana Göhringer:
RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs. 1-8 - Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia:
Robust bitstream protection in FPGA-based systems through low-overhead obfuscation. 1-8 - Wen Wang, Jakub Szefer, Ruben Niederhagen:
Solving large systems of linear equations over GF(2) on FPGAs. 1-7 - Thomas B. Preußer, Markus Krause:
Survey on and re-evaluation of wide adder architectures on FPGAs. 1-6 - Benjamin R. Buhrow, William J. Goetzinger, Barry K. Gilbert:
1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs. 1-8 - Thomas B. Preußer, Martin Zabel, Patrick Lehmann, Rainer G. Spallek:
The portable open-source IP core and utility library PoC. 1-6 - Steffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey:
The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs. 1-7 - Sebastian Meisner, Marco Platzner:
Thread shadowing: On the effectiveness of error detection at the hardware thread level. 1-8 - Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So:
Towards FPGA-assisted spark: An SVM training acceleration case study. 1-6
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